Abstract: The disclosure describes a memory system having a large bit capacity, capable of detecting, locating, and correcting errors. The memory is subdivided into several identical storage matrices wherein parity calculations are performed in the vertical direction within a matrix and in the horizontal direction across a series of matrices. The system also has provision for self-repairs.

Abstract: A computer system is provided for reconstructing a word, which is altered during cycling of the computer memory when a nuclear event occurs. The computer system includes a nuclear event detector, a circuit for setting flags in response to the detection of an event, a generating circuit for generating a random variable time interval in response to the flags, a circuit for performing block parity on the data in the memory in response to the flags, and correcting circuit for correcting the altered word in the memory in response to the block parity circuit. The computer system further includes a circuit for correcting multiple memory word upsets in response to the block parity circuit and an updating circuit for performing block parity during sequential storage or random storage of the data words before or after an event.