Abstract: In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding.

Abstract: In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically In software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding.

Abstract: In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding.

Abstract: In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding.

Abstract: In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding.

Abstract: In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding.

Abstract: A page mapping system for virtual memory that requires only one address to be continually resident in memory per user subspace and permits the size of a process subspace to be varied dynamically. The system provides a tree of page map pages ("PM pages") with only the very root of the tree (a base address entry) being required to be in physical memory. Depending on the size of the space, the page map includes, as well as the base address entry, a number of paged levels with one PM page at the highest level (to which PM page the base address entry points). The page map entries (PMEs) of the first level PM pages point directly to the physical pages. Each PME in a higher level of the page map points to a PM page at a lower level in the page map, whereupon the page map may grow geometrically from the highest level to the first level. The PMEs for pages or PM pages that are not allocated are so marked.

Abstract: A data processing system in which interleaving among memory controllers may be controlled. The interleaving is carried out on a double-word basis, and the state of the double-word address bit is used to select the bus address of the memory controller in which double-words having that address bit are stored. The dynamically controllable interleaving allows greater flexibility in the design of the memory controllers in a data processing system.