Abstract: The present invention is a method and apparatus to synchronize multiple switching regulators in out of phase mode without a phase locked loop. In the present invention, each multiple slave device is connected to a master device and to one another in series, as well as connected to a master clock signal. After a DH, LX or DL output from a preceding device is detected by a following connected slave device, the first subsequent edge of a master clock signal serves to reset the internal clock of the slave device. Each slave device in turn, drives a separate power MOSFET pair in out of phase mode, based upon the output of the preceding device and synchronized to the master clock signal. In the case of multiple regulators, synchronization may be used to reduce electronic noise levels or confine noise to known non-sensitive frequency bands.