Patents by Inventor Len Tsou

Len Tsou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Process and system for etching doped silicon
    Publication number: 20070056927
    Abstract: A process and system for anisoptropically dry etching through a doped silicon layer is described. The process chemistry comprises a nitrogen containing gas and a fluorocarbon gas. For example, the process chemistry comprises CF4, C4F8 and N2.
    Type: Application
    Filed: September 14, 2005
    Publication date: March 15, 2007
    Inventors: Len Tsou, Rajiv Ranade, George Kaplita, Hongwen Yan, Rich Wise, Akiteru Ko
  • Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch
    Patent number: 6528363
    Abstract: A method of forming a notched gate structure having substantially vertical sidewalls and a sub-0.05 &mgr;m electrical critical dimension is provided. The method includes forming a conductive layer on an insulating layer; forming a mask on the conductive layer so as to at least protect a portion of the conductive layer; anisotropically etching the conductive layer not protected by the mask so as to thin the conductive layer to a predetermined thickness and to form a conductive feature underlying the mask, the conductive feature having substantially vertical sidewalls; forming a passivating layer at least on the substantially vertical sidewalls; and isotropically etching remaining conductive layer not protected by the mask to remove the predetermined thickness thereby exposing a lower portion of said conductive feature not containing the passivating layer, while simultaneously removing notched regions in the lower portion of the conductive feature.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: March 4, 2003
    Assignee: International Business Machines Corporation
    Inventors: Victor Ku, Maheswaran Surendra, Len Tsou, Ying Zhang
  • Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch
    Publication number: 20020132394
    Abstract: A method of forming a notched gate structure having substantially vertical sidewalls and a sub-0.05 &mgr;m electrical critical dimension is provided. The method includes forming a conductive layer on an insulating layer; forming a mask on the conductive layer so as to at least protect a portion of the conductive layer; anisotropically etching the conductive layer not protected by the mask so as to thin the conductive layer to a predetermined thickness and to form a conductive feature underlying the mask, the conductive feature having substantially vertical sidewalls; forming a passivating layer at least on the substantially vertical sidewalls; and isotropically etching remaining conductive layer not protected by the mask to remove the predetermined thickness thereby exposing a lower portion of said conductive feature not containing the passivating layer, while simultaneously removing notched regions in the lower portion of the conductive feature.
    Type: Application
    Filed: March 19, 2001
    Publication date: September 19, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Victor Ku, Maheswaran Surendra, Len Tsou, Ying Zhang