Patents by Inventor Lena Peterson

Lena Peterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High performance clock-powered logic
    Patent number: 7626425
    Abstract: High performance clock-powered logic runs at below supply levels and reduces the need for faster digital logic circuitry. In a preferred embodiment, a clocked buffer is used to drive the signal line. The receiving end of the line is connected to a jam latch, preferably followed by an n-latch, followed by the digital logic, and followed by a second n-latch. The first n-latch is eliminated in an alternate embodiment, preferably one that uses complementary data signals.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: December 1, 2009
    Assignee: University of Southern California
    Inventors: William C. Athas, Nestor Tzartzanis, Weihua Mao, Lena Peterson
  • High performance clock-powered logic
    Publication number: 20070018689
    Abstract: High performance clock-powered logic runs at below supply levels and reduces the need for faster digital logic circuitry. In a preferred embodiment, a clocked buffer is used to drive the signal line. The receiving end of the line is connected to a jam latch, preferably followed by an n-latch, followed by the digital logic, and followed by a second n-latch. The first n-latch is eliminated in an alternate embodiment, preferably one that uses complementary data signals.
    Type: Application
    Filed: January 13, 2006
    Publication date: January 25, 2007
    Applicant: University of Southern California
    Inventors: William Athas, Nestor Tzartzanis, Weihua Mao, Lena Peterson
  • High-performance clock-powered logic
    Patent number: 7005893
    Abstract: High performance clock-powered logic runs at below supply levels and reduces the need for faster digital logic circuitry. In a preferred embodiment, a clocked buffer (101) is used to drive the signal line. The receiving end of the line is connected to a jam latch (123), preferably followed by an n-latch (125), followed by the digital logic (109), and followed by a second n-latch (127). The first n-latch is eliminated in an alternative embodiment, preferably one that uses complementary data signals.
    Type: Grant
    Filed: July 18, 2000
    Date of Patent: February 28, 2006
    Assignee: University of Southern California
    Inventors: William C. Athas, Nestor Tzartzanis, Weihua Mao, Lena Peterson