Abstract: A switched capacitor circuit employs a single operational amplifier to implement both an integrator and a summer. One input signal is routed to the input of the operational amplifier through (1) one or more integration branches, and (2) one or more first summing branches. A second input signal is routed to the input of the operational amplifier through one or more second summing branches. Each of the branches includes a capacitor and a number of switches controlled by different clock phases. The switched capacitor circuit may be single-ended or differential. The circuit may be used in an access terminal of a cellular communication system. The access terminal may operate under a code division multiple access (CDMA) communication standard.

Abstract: Techniques for efficiently generating a power supply are described. In one design, an apparatus includes an envelope amplifier and a boost converter. The boost converter generates a boosted supply voltage having a higher voltage than a first supply voltage (e.g., a battery voltage). The envelope amplifier generates a second supply voltage based on an envelope signal and the boosted supply voltage (and also possibly the first supply voltage). A power amplifier operates based on the second supply voltage. In another design, an apparatus includes a switcher, an envelope amplifier, and a power amplifier. The switcher receives a first supply voltage and provides a first supply current. The envelope amplifier provides a second supply current based on an envelope signal. The power amplifier receives a total supply current including the first and second supply currents. In one design, the switcher detects the second supply current and adds an offset to generate a larger first supply current than without the offset.

Abstract: Techniques for efficiently generating a power supply are described. In one design, an apparatus includes an envelope amplifier and a boost converter. The boost converter generates a boosted supply voltage having a higher voltage than a first supply voltage (e.g., a battery voltage). The envelope amplifier generates a second supply voltage based on an envelope signal and the boosted supply voltage (and also possibly the first supply voltage). A power amplifier operates based on the second supply voltage. In another design, an apparatus includes a switcher, an envelope amplifier, and a power amplifier. The switcher receives a first supply voltage and provides a first supply current. The envelope amplifier provides a second supply current based on an envelope signal. The power amplifier receives a total supply current including the first and second supply currents. In one design, the switcher detects the second supply current and adds an offset to generate a larger first supply current than without the offset.

Abstract: A method and apparatus for avoiding receiver interference is described herein. One or more potential interferers are determined and the frequency associated with the interferers is also determined A desired sampling frequency for the receiver is calculated to avoid the potential interferers.

Abstract: A combinatorial circuit with pre-calculation and having shorter delay is described. The combinatorial circuit uses information available from earlier input signals to pre-calculate intermediate signals, which are used to generate output signals when the last input signal arrives. The combinatorial circuit includes an input calculation block, at least one pre-calculation block, and an output calculation block coupled in series. The input calculation block receives some input signals and generates intermediate signals for the first pre-calculation block. The pre-calculation block(s) receive at least one earlier input signal and generate additional intermediate signals. The output calculation block receives the latest input signal and the intermediate signals from the last pre-calculation block and generates the output signals. The pre-calculation block(s) and the output calculation block may be implemented with simple circuits.

Abstract: All-digital techniques for generating periodic digital signals having selectable duty cycles. In one aspect, a computation block is provided for computing the product of a selected duty cycle and a discrete ratio between a reference clock period and a high-frequency oscillator period. The computation block may be coupled to a pulse width generator for generating signals having pulse widths that are integer multiples of the high-frequency oscillator period. In another aspect, a pulse width generator may also accommodate mixed fractional multiples of high-frequency oscillator periods by tapping the individual inverter stages of a delay line matched to the individual inverter stages of a ring oscillator exemplary embodiment of the high-frequency oscillator.

Abstract: Exemplary embodiments of the invention disclose signal filtering. In an exemplary embodiment, a filter device may comprise a subtractor operably coupled between an input and an output and configured to receive an input signal comprising a desired component and at least one undesired frequency component. The filter device may further include a feedback loop configured to receive at least one of the input signal and an output signal from the subtractor and convey a feedback signal comprising at least one undesired component to the subtractor. Each undesired component of the feedback signal corresponds to an associated undesired component of the input signal. Furthermore, the subtractor subtracts the feedback signal from the input signal and convey the output signal.

Abstract: A successive approximation analog-to-digital converter (ADC) includes a binary-weighted capacitor array, quantizer, and control block. One end of each capacitor is connected to the input of the quantizer, and a second end of each capacitor is controlled by the control block through a driver. A voltage is sampled, quantized, and stored as the most significant bit of the ADC's output. Depending on the result of the quantization, the control block toggles the driver of one of the capacitors corresponding to the most significant bit. The voltage at the common node is sampled again to obtain a second bit of the ADC's output. The operations are repeated as needed to obtain and store additional bits of the ADC's output. Similar configuration and process are described for a differential ADC. The operation is asynchronous, allowing extra time for metastable states only when such states occur.

Abstract: A combinatorial circuit with pre-calculation and having shorter delay is described. The combinatorial circuit uses information available from earlier input signals to pre-calculate intermediate signals, which are used to generate output signals when the last input signal arrives. The combinatorial circuit includes an input calculation block, at least one pre-calculation block, and an output calculation block coupled in series. The input calculation block receives some input signals and generates intermediate signals for the first pre-calculation block. The pre-calculation block(s) receive at least one earlier input signal and generate additional intermediate signals. The output calculation block receives the latest input signal and the intermediate signals from the last pre-calculation block and generates the output signals. The pre-calculation block(s) and the output calculation block may be implemented with simple circuits.

Abstract: A method and apparatus for avoiding receiver interference is described herein. One or more potential interferers are determined and the frequency associated with the interferers is also determined A desired sampling frequency for the receiver is calculated to avoid the potential interferers.

Abstract: All-digital techniques for generating periodic digital signals having selectable duty cycles. In one aspect, a computation block is provided for computing the product of a selected duty cycle and a discrete ratio between a reference clock period and a high-frequency oscillator period. The computation block may be coupled to a pulse width generator for generating signals having pulse widths that are integer multiples of the high-frequency oscillator period. In another aspect, a pulse width generator may also accommodate mixed fractional multiples of high-frequency oscillator periods by tapping the individual inverter stages of a delay line matched to the individual inverter stages of a ring oscillator exemplary embodiment of the high-frequency oscillator.

Abstract: Exemplary embodiments of the invention disclose signal filtering. In an exemplary embodiment, a filter device may comprise a subtractor operably coupled between an input and an output and configured to receive an input signal comprising a desired component and at least one undesired frequency component. The filter device may further include a feedback loop configured to receive at least one of the input signal and an output signal from the subtractor and convey a feedback signal comprising at least one undesired component to the subtractor. Each undesired component of the feedback signal corresponds to an associated undesired component of the input signal.

Abstract: The present patent application comprises a digital to analog converter reference circuit, comprising a capacitor connected to a current source, a positive terminal of the capacitor connected to a first switch, the first switch electrically connecting the positive terminal of the capacitor to a positive input terminal of a DAC circuit, a negative terminal of the capacitor connected to a second switch, the second switch electrically connecting the negative terminal of the capacitor to a negative input terminal of the DAC circuit. In another example, the present patent application comprises a method for converting digital code to an analog signal, comprising charging a reservoir capacitor to a reference voltage level, transferring stored charge from the reservoir capacitor to DAC feedback capacitors, and transferring the stored charge from the DAC feedback capacitors to DAC output terminals.

Abstract: Techniques for enhancing the slew rate of an active circuit within a feedback circuit (such as a ?? ADC) are described. In one design, a ?? ADC includes an integrator, a slew rate enhancement circuit, and a control circuit. The integrator receives an input signal and provides an output signal. The slew rate enhancement circuit enhances the slew rate of the integrator based on a feedback signal in the ?? ADC. The slew rate enhancement circuit may provide (i) a boost current for only certain values (e.g., the largest and smallest values) of the feedback signal or (ii) different amounts of boost current for different values of the feedback signal. In one design, the slew rate enhancement circuit includes at least one boost circuit coupled to the integrator. Each boost circuit provides a boost current to enhance the slew rate of the integrator when that boost circuit is enabled.

Abstract: A successive approximation analog-to-digital converter (ADC) includes a binary-weighted capacitor array, quantizer, and control block. One end of each capacitor is connected to the input of the quantizer, and a second end of each capacitor is controlled by the control block through a driver. A voltage is sampled, quantized, and stored as the most significant bit of the ADC's output. Depending on the result of the quantization, the control block toggles the driver of one of the capacitors corresponding to the most significant bit. The voltage at the common node is sampled again to obtain a second bit of the ADC's output. The operations are repeated as needed to obtain and store additional bits of the ADC's output. Similar configuration and process are described for a differential ADC. The operation is asynchronous, allowing extra time for metastable states only when such states occur.

Abstract: A switched capacitor circuit employs a single operational amplifier to implement both an integrator and a summer. One input signal is routed to the input of the operational amplifier through (1) one or more integration branches, and (2) one or more first summing branches. A second input signal is routed to the input of the operational amplifier through one or more second summing branches. Each of the branches includes a capacitor and a number of switches controlled by different clock phases. The switched capacitor circuit may be single-ended or differential. The circuit may be used in an access terminal of a cellular communication system. The access terminal may operate under a code division multiple access (CDMA) communication standard.

Abstract: Techniques for enhancing the slew rate of an active circuit within a feedback circuit (such as a ?? ADC) are described. In one design, a ?? ADC includes an integrator, a slew rate enhancement circuit, and a control circuit. The integrator receives an input signal and provides an output signal. The slew rate enhancement circuit enhances the slew rate of the integrator based on a feedback signal in the ?? ADC. The slew rate enhancement circuit may provide (i) a boost current for only certain values (e.g., the largest and smallest values) of the feedback signal or (ii) different amounts of boost current for different values of the feedback signal. In one design, the slew rate enhancement circuit includes at least one boost circuit coupled to the integrator. Each boost circuit provides a boost current to enhance the slew rate of the integrator when that boost circuit is enabled.

Abstract: The present patent application comprises a digital to analog converter reference circuit, comprising a capacitor connected to a current source, a positive terminal of the capacitor connected to a first switch, the first switch electrically connecting the positive terminal of the capacitor to a positive input terminal of a DAC circuit, a negative terminal of the capacitor connected to a second switch, the second switch electrically connecting the negative terminal of the capacitor to a negative input terminal of the DAC circuit. In another example, the present patent application comprises a method for converting digital code to an analog signal, comprising charging a reservoir capacitor to a reference voltage level, transferring stored charge from the reservoir capacitor to DAC feedback capacitors, and transferring the stored charge from the DAC feedback capacitors to DAC output terminals.