Abstract: A voltage burst is generated using a voltage supply having a single DC output voltage, VH coupled with a switching arrangement, including an input and a voltage transmitter output (Tx_Out), the input coupled with the output of the voltage supply. A control arrangement coupled with the switching arrangement is configured to operate the switching arrangement so as to provide, at the Tx_Out, a voltage burst that varies between an intermediate voltage, VM, and one or both of VH, and a minimum voltage, VL, where VL<VM<VH.

Abstract: In certain aspects, a bias generation circuit comprises a bias voltage generator. The bias voltage generator has a main NMOS transistor having a drain and a gate of the main NMOS transistor both coupled to a first terminal, a main resistor having a first main resistor terminal and a second main resistor terminal, wherein the first main resistor terminal couples to a source of the main NMOS transistor; and a main PMOS transistor having a source of the main PMOS transistor coupled to the second main resistor terminal and a drain and a gate of the main PMOS transistor both coupled to a second terminal, wherein the second terminal couples to a main ground. The bias generation circuit further comprises an array of sensors coupled to the first terminal and the second terminal.

Abstract: An apparatus and method for efficiently increasing the signal-to-noise ratio of a biometric sampling system by implementing differential-sampling in successive differential-sampling operations and processing the output of the successive differential-sampling operations to create a biometric image. In some cases, the biometric image may be further noise-reduced by subtracting foreground-off and background-off data.

Abstract: The present disclosure describes aspects of a capacitance-to-voltage modulation circuit. In some aspects, the circuit is used in touch sensing. In some aspects, a modulation circuit comprises a first pair of switches having one switch connected between a voltage source and a capacitor, and another switch connected between ground and the input of the circuit. The circuit also includes a second pair of switches having one switch connected between the voltage source and the input of the circuit, and another switch connected between ground and the capacitor. A third pair of the circuit's switches comprise one switch connected between the capacitor and an input of an analog-to-digital converter (ADC) and another switch connected between the input of the circuit and the input of the ADC. The third pair of switches may enable charge sharing of signals modulated by the first and second pairs of switches, a result of which can be used to sense touch input based on capacitance at the input of the circuit.

Abstract: The present disclosure describes aspects of a capacitance-to-voltage modulation circuit. In some aspects, the circuit is used in touch sensing. In some aspects, a modulation circuit comprises a first pair of switches having one switch connected between a voltage source and a capacitor, and another switch connected between ground and the input of the circuit. The circuit also includes a second pair of switches having one switch connected between the voltage source and the input of the circuit, and another switch connected between ground and the capacitor. A third pair of the circuit's switches comprise one switch connected between the capacitor and an input of an analog-to-digital converter (ADC) and another switch connected between the input of the circuit and the input of the ADC. The third pair of switches may enable charge sharing of signals modulated by the first and second pairs of switches, a result of which can used to sense touch input based on capacitance at the input of the circuit.

Abstract: Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. A non-overlapping clock generation circuit comprises a delay lock loop (DLL) circuit that generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. The clock generator circuit may also include voltage-controlled delay cells that generate sets of clock signals delayed from one another by a non-overlapping time (tnlp).

Abstract: A discrete-time operational transconductance amplifier (OTA) with large gain and large output signal swing is described. In an exemplary design, the discrete-time OTA includes a clocked comparator and an output circuit. The clocked comparator receives an input voltage and provides a digital comparator output. The output circuit receives the digital comparator output and provides current pulses. The output circuit detects for changes in the sign of the input voltage based on the digital comparator output and reduces the amplitude of the current pulses when a change in the sign of the input voltage is detected. The output circuit also generates the current pulses to have a polarity that is opposite of the polarity of the input voltage. The discrete-time OTA may be used for switched-capacitor circuits and other applications.

Abstract: Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. A non-overlapping clock generation circuit comprises a delay lock loop (DLL) circuit that generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. The clock generator circuit may also include voltage-controlled delay cells that generate sets of clock signals delayed from one another by a non-overlapping time (tnlp).

Abstract: Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. In one configuration, a device includes a non-overlapping clock generation circuit which comprises a delay lock loop (DLL) circuit that in turn generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. In a further aspect, the clock generator circuit includes a plurality of voltage-controlled delay cells coupled to the DLL circuit to generate a first set of clock signals and a second set of clock signals delayed from the first set of clock signals by a non-overlapping time (tnlp) that is independent of manufacturing process variations.

Abstract: A discrete-time operational transconductance amplifier (OTA) with large gain and large output signal swing is described. In an exemplary design, the discrete-time OTA includes a clocked comparator and an output circuit. The clocked comparator receives an input voltage and provides a digital comparator output. The output circuit receives the digital comparator output and provides current pulses. The output circuit detects for changes in the sign of the input voltage based on the digital comparator output and reduces the amplitude of the current pulses when a change in the sign of the input voltage is detected. The output circuit also generates the current pulses to have a polarity that is opposite of the polarity of the input voltage. The discrete-time OTA may be used for switched-capacitor circuits and other applications.

Abstract: Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. In one configuration, a device includes a non-overlapping clock generation circuit which comprises a delay lock loop (DLL) circuit that in turn generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. In a further aspect, the clock generator circuit includes a plurality of voltage-controlled delay cells coupled to the DLL circuit to generate a first set of clock signals and a second set of clock signals delayed from the first set of clock signals by a non-overlapping time (tnlp) that is independent of manufacturing process variations.

Abstract: Systems and methods are provided for reducing the peak to average ratio of signals, so that the signals can be amplified more efficiently. An error signal that corresponds to crests of the input signal is generated, and subtracted from the input signal. When a crest is so long that it corresponds to more than one sample, only the maximum sample contained in the crest is used to form the error signal. Optionally, multiple stages of decresting may be implemented sequentially.

Abstract: Bandwidth reduction of amplitude and/or phase components of relatively wide bandwidth composite signal. In an exemplary embodiment, an EER amplifier system for CDMA signal amplification includes an amplitude bandwidth reduction module included in an amplitude signal component path and a phase bandwidth reduction module is included in a phase signal component path, for controlling an RF amplifier. The phase bandwidth reduction module may reduce the phase component bandwidth of the input signal by, for example, generating a non-linear relationship between phase signal amplitude and input signal amplitude. The amplitude bandwidth reduction module may reduce the amplitude component bandwidth of the input signal by, for example, generating a non-linear relationship between the supply voltage to the RF amplifier and an input signal amplitude.

Abstract: A dual feedback topology imparts stability to a multistage linear amplifier, particularly by improving overall amplifier phase margin at higher signal frequencies. With dual feedback, an inner feedback loop is closed around the first amplifier stage, which stage is configured as a current feedback amplifier. A second feedback loop is closed around the overall multistage amplifier. With a current feedback amplifier as the initial stage, the two feedback signals are current-mode signals and thus add to form the combined feedback signal. The frequency responses of the inner and outer feedback loops may be tailored for flat frequency response, or, where desired, may be adjusted to compensate or otherwise flatten overall amplifier frequency response.

Abstract: A low power programmable digital filter adapted for use with a telecommunications system transceiver. The digital filter includes a first finite impulse response filter section for receiving an input signal and having a first transfer function. An infinite impulse response filter section is connected to the first finite impulse response filter section and has a second transfer function. A second finite impulse response filter section is connected to the infinite impulse response filter section and outputs a filtered output signal in response the receipt of the input signal by the programmable digital filter. The second finite impulse response filter section has a third transfer function. A programmable coefficient is included in the first, second, and/or the third transfer function.

Abstract: A biasing circuit for biasing a device (e.g., a GaAs field effect transistor) used for amplifying a radio frequency (RF) signal, the biasing circuit including an active element in series with a resistor, the active element providing a relatively low impedance over a bandwidth comparable to an amplitude modulation bandwidth of the RF signal, such that a DC bias voltage applied at the active element has a fixed DC voltage at the resistor input, i.e., without any memory effect, thereby allowing for improved predistortion compensation of non-linear voltage of the RF signal.

Abstract: An error amplifier circuit reduces distortion in an amplified signal by reflecting a feedback signal into the amplified signal using an output transformer. A first amplifier generates a reference signal corresponding to the input signal from which the amplifier output signal is derived. This reference signal represents the desired waveform for the amplified signal. An error sense element generates an error signal based on the difference between the reference and amplified signals. The error sense element preferably imparts high common-mode rejection to the error signal. A second amplifier generates the feedback signal based on amplifying the error signal, and an output transformer generates a compensated amplified signal by coupling the feedback signal into the amplified signal. The output transformer increases the reflected load impedance seen by the error amplifier, thus relieving it from driving the feedback signal into the potentially low load impedance driven by the compensated amplified signal.

Abstract: A wideband precision current sensor employs DC-coupled and AC-coupled sensing circuits to generate lower and higher frequency sense signals; which are combined to form a wideband output signal that is proportional to a wideband current of interest. The frequency response of the wideband output signal is substantially flat across a wideband frequency range, 0 to 30 MHz for example, based on matching the frequency response of the DC- and AC-coupled sensing circuits. In an exemplary application, the current sensor provides feedback to a supply voltage (Vdd) amplifier used in RF envelope elimination and restoration (EER) applications.

Abstract: A dual feedback topology imparts stability to a multistage linear amplifier, particularly by improving overall amplifier phase margin at higher signal frequencies. With dual feedback, an inner feedback loop is closed around the first amplifier stage, which stage is configured as a current feedback amplifier. A second feedback loop is closed around the overall multistage amplifier. With a current feedback amplifier as the initial stage, the two feedback signals are current-mode signals and thus add to form the combined feedback signal. The frequency responses of the inner and outer feedback loops may be tailored for flat frequency response, or, where desired, may be adjusted to compensate or otherwise flatten overall amplifier frequency response.

Abstract: A wideband precision current sensor employs DC-coupled and AC-coupled sensing circuits to generate lower and higher frequency sense signals, which are combined to form a wideband output signal that is proportional to a wideband current of interest. The frequency response of the wideband output signal is substantially flat across a wideband frequency range, 0 to 30 MHz for example, based on matching the frequency response of the DC- and AC-coupled sensing circuits. In an exemplary application, the current sensor provides feedback to a supply voltage (Vdd) amplifier used in RF envelope elimination and restoration (EER) applications.