Abstract: A method and system are provided that minimize wafer or package level test time without adversely impacting yields in downstream manufacturing processes or degrading outgoing quality levels. The method provides optimization by determining, a priority, the most effective set of tests for a given lot or wafer. The invention implements a method using a processor-based system involving the integration of multiple sources of data that include: historical and realtime, product specific and lot specific, from wafer fabrication data (i.e., process measurements, defect inspections, and parametric testing), product qualification test results, physical failure analysis results and manufacturing functional test results. These various forms of data are used to determine an optimal set of tests to run using a test application sequence, on a given product to optimize test time with minimum risk to yield or product quality.

Abstract: A method and system are provided that minimize wafer or package level test time without adversely impacting yields in downstream manufacturing processes or degrading outgoing quality levels. The method provides optimization by determining, a priority, the most effective set of tests for a given lot or wafer. The invention implements a method using a processor-based system involving the integration of multiple sources of data that include: historical and realtime, product specific and lot specific, from wafer fabrication data (i.e., process measurements, defect inspections, and parametric testing), product qualification test results, physical failure analysis results and manufacturing functional test results. These various forms of data are used to determine an optimal set of tests to run using a test application sequence, on a given product to optimize test time with minimum risk to yield or product quality.

Abstract: A method for testing high I/O chips on low I/O testers is provided. Chips having programmable I/Os are used with an interface board that shorts groups of I/Os to a single tester channel. Patterns are provided to the chip to enable one I/O of each group at a time, thereby allowing all I/Os in each group to be tested sequentially. Thus, a multiplexing function is divided between the chip itself and the interface board.

Abstract: A method of dynamically modifying a test program makes testing more efficient and less costly while avoiding errors from manual operations. In one embodiment the order of functional tests in the test program is dynamically changed based on the results of testing. Tests that have caused fails are moved earlier in the testing program without having to recompile the test program. Each functional test has an initialization step to set the chip in a state from which subsequent test vectors are run.

Abstract: An animal body parts phantom comprised of a substrate sheet which is shaped in the form of an animal body part e.g. a thyroid, including a radioactive material substantially uniformly deposited on the substrate, and a tissue simulating material encapsulating and supporting the substrate. A container may be included to provide a mold for the tissue simulating material and to protect the phantom. An additional fat simulating overlay may also be provided to extend the capability of the device.