Abstract: Disclosed is a self-isolating cross-coupled sense amplifier latch circuit having five enhancement mode field effect transistor devices and two depletion mode field effect transistor devices. The first and second field effect transistors form a cross-coupled pair with true and complement outputs being available at the cross-coupled nodes. A third field effect transistor is connected to a common connection between the source electrodes of the cross-coupled pair and is used to establish a race condition after a small difference in potential has been applied to the aforementioned output nodes. A pair of depletion mode devices are connected as diodes between a positive potential (VH) and each of the output nodes, respectively. Each of the output nodes is connected to a respective bit line of a column of memory cells through enhancement mode field effect transistors connected as third and fourth unidirectionally conducting devices.

Abstract: A circuit comprising the parallel connection of an enhancement-and a depletion-type FET which exhibits reduced power and improved performance for both logic as well as memory circuits.

Abstract: A split random access memory array is integrated with a read only storage array and shares the same sense and bit decode circuitry. Each bit line of the integrated array is provided with an isolation switch between the random access and read only portions. The switch conducts when reading the read only portion but does not conduct (isolates) when writing or reading the random access portion. The isolation switch also permits the initialization of the shared differential sensing latch and facilitates the rapid writing and reading of the random access portion by removing the bit line loading due to the read only portion on such occasions.