Patents by Inventor Leo Craft

Leo Craft has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250076156
    Abstract: A testing device, related method for using the testing device and a production device arranged based on a predicted ambient temperature determined using the testing device, the testing device including a circuitry of a first form factor that corresponds to a second form factor of the production device. Circuitry includes heat-generating electrical components to simulate thermal generation of the production device. The circuitry also includes sensors to measure at least one characteristic of airflow of the testing device and at least one temperature of the testing device. The sensors include a first sensor disposed upstream of the airflow, and a second sensor disposed downstream of the airflow. The circuitry also includes processing circuitry to receive sensor data from the sensors indicative the characteristics of airflow and the temperatures of the testing device, and to determine a predicted ambient temperature proximate to the production device based on the sensor data.
    Type: Application
    Filed: August 29, 2023
    Publication date: March 6, 2025
    Inventors: Hardeep Singh, Leo Craft
  • Patent number: 10573575
    Abstract: Embodiments of the present disclosure provide techniques and configurations for a semiconductor package with thermal fins, in accordance with some embodiments. In embodiments, a package assembly includes a die and a mold compound disposed on the die, to encapsulate the die. The package may further include a thermal solution including one or more thermal fins attached to the mold compound at their respective ends. The thermal fins may be disposed substantially flat on a top surface of the mold compound at a first temperature, and rise away from the top surface of the mold compound in response to a change of temperature to a second temperature, to reach an enclosure that surrounds the package assembly, to provide direct heat conductivity between the die and the enclosure. The second temperature may be greater than the first temperature. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: Hyoung Il Kim, Florence Pon, Yi Xu, Yuhong Cai, Min-Tih Lai, Leo Craft
  • Publication number: 20190067156
    Abstract: Embodiments of the present disclosure provide techniques and configurations for a semiconductor package with thermal fins, in accordance with some embodiments. In embodiments, a package assembly may comprise a die and a mold compound disposed on the die, to encapsulate the die. The package may further include a thermal solution comprising one or more thermal fins attached to the mold compound at their respective ends. The thermal fins may be disposed substantially flat on a top surface of the mold compound at a first temperature, and rise away from the top surface of the mold compound in response to a change of temperature to a second temperature, to reach an enclosure that surrounds the package assembly, to provide direct heat conductivity between the die and the enclosure. The second temperature may be greater than the first temperature. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: August 28, 2017
    Publication date: February 28, 2019
    Inventors: Hyoung Il Kim, Florence Pon, Yi Xu, Yuhong Cai, Min-Tih Lai, Leo Craft
  • Patent number: 6098283
    Abstract: A via for an electronic assembly. The assembly includes a substrate which has a via hole. The via hole is filled with a conductive material that extends across a diameter of the hole. The via hole can be filled by reflowing a solder ball that is attached to an outer surface of the substrate. The substrate may be part of a multi-layered integrated circuit package, wherein the vias couples internal routing layers with external contacts of the package. The filled vias can withstand extended thermal life cycles of the package.
    Type: Grant
    Filed: May 13, 1998
    Date of Patent: August 8, 2000
    Assignee: Intel Corporation
    Inventors: Mike Goetsch, Jim Siettmann, Leo Craft, Eric Swanger