Patents by Inventor Leo D. Yau

Leo D. Yau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5212910
    Abstract: An improved composite polishing pad includes a first layer of elastic material, a second, stiff layer and a third layer optimized for slurry transport. This third layer is the layer against which the wafer makes contact during the polishing process. The second layer is segmented into individual sections physically isolated from one another in the lateral dimension. Each segmented section is resilient across its width yet cushioned by the first layer in the vertical direction. The physical isolation of each section combined with the cushioning of the first layer of material create a sort of "bedspring" effect which enables the pad to conform to longitudinal gradations across the wafer.
    Type: Grant
    Filed: July 9, 1991
    Date of Patent: May 25, 1993
    Assignee: Intel Corporation
    Inventors: Joseph R. Breivogel, Sam F. Louke, Michael R. Oliver, Leo D. Yau
  • Patent number: 4536947
    Abstract: A CMOS process is described which is particularly suited for forming dynamic memory cells. The cells are formed in an n-well and a single plate member formed from a first layer of polysilicon is used for the entire array. Unique etching of the first polysilicon layer prevents stringers from occurring when the second layer of polysilicon is deposited. A tri-layer dielectric is used for the capacitors in the array. Novel "rear-end" processing is disclosed using a phosphorus doped glass.
    Type: Grant
    Filed: July 2, 1984
    Date of Patent: August 27, 1985
    Assignee: Intel Corporation
    Inventors: Mark T. Bohr, Ken K. Yu, Leo D. Yau, Shyam G. Garg
  • Patent number: 4505026
    Abstract: A CMOS process is described which is particularly suited for forming dynamic memory cells. The cells are formed in an n-well and a single plate member formed from a first layer of polysilicon is used for the entire array. Unique etching of the first polysilicon layer prevents stringers from occurring when the second layer of polysilicon is deposited. A tri-layer dielectric is used for the capacitors in the array. Novel "rear-end" processing is disclosed using a phosphorus doped glass.
    Type: Grant
    Filed: July 14, 1983
    Date of Patent: March 19, 1985
    Assignee: Intel Corporation
    Inventors: Mark T. Bohr, Ken K. Yu, Leo D. Yau, Shyam G. Garg