Abstract: Technologies directed to grant-free transmission communication methodology and systems are described. One method includes determining first data that is associated with data transmission between a communication device and a first user terminal (UT). The method further includes determining, based on the first data, second data. The second data indicates communication resources associated with an uplink to the communication system that is allocated to the first UT. The second data further indicates that the communication resources are available for sending additional data by other non-scheduled UTs. The method further includes sending the second data to the first UT and receiving third data using the communication resources. The method further includes identifying a first portion of the third data that is associated with data transmission by a second UT. The method further includes identifying a second portion of the third data that is associated with data transmission by the first UT.

Abstract: Technologies directed to co-channel interference detection using a signal correlation test are described. One method includes receiving a radio frequency (RF) signal and generating digital sample corresponding to the RF signal. The method further includes determining a first correlation coefficient using the digital samples, a first value, and a second value. The first value corresponds to a signal lag parameter and the second value corresponds to a cyclic frequency parameter. The method further includes determining a second correlation coefficient using the digital samples, the first value, and a third value corresponding to the cyclic frequency parameter. The second value and the third value are multiples of a fourth value. The method further includes determining, using the first correlation coefficient and the second correlation coefficient, that first RF signal comprises a first portion from a second communication device and a second portion from a third communication device.

Abstract: A constellation of many satellites and associated ground stations provide communication service to user terminals. These devices use modulation techniques such as orthogonal frequency division multiplexing (OFDM) to send large quantities of data. For transmission, a power amplifier increases the amplitude of a waveform modulated in this way. The power amplifier operates more efficiently closer to saturation. However, operation at saturation results in nonlinear distortion, producing unwanted signals and increasing bit error rate. A set of techniques are used to reduce the peak to average power ratio (PAPR) of the waveform provided to the power amplifier. A distortionless technique remaps blocks of bits to reduce the resulting PAPR of that block. Additional techniques may also be progressively applied to reduce PAPR while minimizing adverse consequences such as in-band distortion, out of band emissions, increased bit error rate, and so forth.

Abstract: A network device comprising: a first connector for connecting to an external network from which data may be communicated using a first frequency band in accordance with a first communications protocol; a second connector for connecting to an on-premises network; and circuitry residing in a signal path between said first connector and said second connector. The circuitry may be operable to: permit a first portion of the first frequency band to pass from the first connector to the second connector; block a second portion of said first frequency band from passing from the first connector to the second connector; and communicate, via the second connector, signals that are normally communicated in frequency ranges not including the first frequency band, into the on-premises network using the first frequency band. The signals may include packets formatted in accordance with Multimedia over Coax Alliance (MoCA) standards.

Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals.

Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals.

Abstract: A network device comprising: a first connector for connecting to an external network from which data may be communicated using a first frequency band in accordance with a first communications protocol; a second connector for connecting to an on-premises network; and circuitry residing in a signal path between said first connector and said second connector. The circuitry may be operable to: permit a first portion of the first frequency band to pass from the first connector to the second connector; block a second portion of said first frequency band from passing from the first connector to the second connector; and communicate, via the second connector, signals that are normally communicated in frequency ranges not including the first frequency band, into the on-premises network using the first frequency band. The signals may include packets formatted in accordance with Multimedia over Coax Alliance (MoCA) standards.

Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is aliased onto a desired signal by a timing offset in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

Abstract: A network device may comprise a first connector for connecting to an external network in which upstream data over cable service interface specification (DOCSIS) signals are communicated using a first frequency band and downstream cable and/or DOCSIS signals are communicated using a second frequency band. The device may also comprise a second connector for connecting to an on-premises network, as well as circuitry residing in a signal path between the first connector and the second connector. The circuitry may be operable to permit the downstream cable and/or DOCSIS signals to pass from the first connector to the second connector, and to block the upstream DOCSIS signals from passing from the first connector to the second connector. The circuitry may be operable to transmit, via the second connector, non-DOCSIS signals into the on-premises network using the first frequency band.

Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is aliased onto a desired signal by a timing offset in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

Abstract: A transmitter comprises a first peak-to-average-power ratio (PAPR) suppression circuit, a second peak-to-average-power ratio (PAPR) suppression circuit, and a first modulator. The first PAPR suppression circuit may receive a first sequence of time-domain symbols to be transmitted, alter the first sequence based on each of a plurality of symbol ordering and/or inversion descriptors to generate a corresponding plurality of second sequences of time-domain symbols, measure a PAPR corresponding to each of the second sequences, select one of the plurality of symbol ordering and/or inversion descriptors based on the measurement of PAPR, and convey the selected one of the symbol ordering and/or inversion descriptors to the second PAPR suppression circuit.

Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

Abstract: A transmitter may comprise a first domain translation circuit, a first PAPR suppression circuit, and a descriptor generation circuit. The first domain translation circuit may convert a plurality of frequency-domain symbols of a first OFDM symbol to a corresponding plurality of first time-domain signals. The first PAPR suppression circuit may group the plurality of first time-domain signals into a plurality of sub-bands of the first time-domain. The first PAPR suppression circuit may invert one or more of the sub-bands of the first time-domain signals according to a value of a first descriptor. The descriptor generation circuit may determine the value of the first descriptor using an iterative process in which each iteration comprises random selection of a value of the first descriptor, determination of a PAPR of the first OFDM symbol processed using the randomly-selected value, and determination of whether said PAPR meets one or more determined criteria.

Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may include a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals.

Abstract: Data is managed in a Host Wireless Adapater (HWA)-Device Wireless Adapater (DWA) system by receiving at the HWA a wireless packet from the DWA which contains a DWA Transfer Result message. At the HWA, the DWA Transfer Result message is parsed. In the event parsing the DWA Transfer Result message indicates there is data ready to be sent over a wireless channel between the HWA to the DWA a Micro-scheduled Management Command (MMC) is generating at the HWA and the MMC is transmitted from the HWA to the DWA. The MMC is transmitted prior to receiving a Transfer Request message at the HWA from an HWA driver and the data is transmitted from the DWA to the HWA in response to receiving the MMC.

Abstract: A transmitter may comprise a first domain translation circuit, a first PAPR suppression circuit, and a descriptor generation circuit. The first domain translation circuit may convert a plurality of frequency-domain symbols of a first OFDM symbol to a corresponding plurality of first time-domain signals. The first PAPR suppression circuit may group the plurality of first time-domain signals into a plurality of sub-bands of the first time-domain. The first PAPR suppression circuit may invert one or more of the sub-bands of the first time-domain signals according to a value of a first descriptor. The descriptor generation circuit may determine the value of the first descriptor using an iterative process in which each iteration comprises random selection of a value of the first descriptor, determination of a PAPR of the first OFDM symbol processed using the randomly-selected value, and determination of whether said PAPR meets one or more determined criteria.

Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals.

Abstract: Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output.

Abstract: An improved slot machine provides a plurality of animated scenes, the outcomes of which determine whether the player has won. The slot machine provides some of the traditional elements of a slot machine but with improved entertainment replacing the spinning reels. Scenes may depict objects that are moving toward a line, which is reminiscent of the line in the traditional slot machine, but in this case represents something physical with which the objects interact. For example, the objects could be birds that are falling/flying down onto a wire. In another example, the objects are freely falling onto the ground or floor. The scenes depict several possible outcomes of the interaction between the objects. Based upon the resulting outcomes (e.g. matching outcomes, like a traditional slot machine) the player wins or loses.