Patents by Inventor Leo Hsu

Leo Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230069302
    Abstract: A butted contact structure is provided. In one embodiment, a structure includes a first transistor on a substrate, the first transistor comprising a first source or drain region, a first gate, and a first gate spacer being disposed between the first gate and the first source or drain region. The structure includes a second transistor on the substrate, the second transistor comprising a second source or drain region, a second gate, and a second gate spacer being disposed between the second gate and the second source or drain region. The structure includes a butted contact disposed above and extending from the first source or drain region to at least one of the first or second gate, a portion of the first gate spacer extending a distance into the butted contact to separate a first bottom surface of the butted contact from a second bottom surface of the butted contact.
    Type: Application
    Filed: October 17, 2022
    Publication date: March 2, 2023
    Inventors: Leo Hsu, Sheng-Liang Pan
  • Patent number: 11476159
    Abstract: A butted contact structure is provided. In one embodiment, a structure includes a first transistor on a substrate, the first transistor comprising a first source or drain region, a first gate, and a first gate spacer being disposed between the first gate and the first source or drain region. The structure includes a second transistor on the substrate, the second transistor comprising a second source or drain region, a second gate, and a second gate spacer being disposed between the second gate and the second source or drain region. The structure includes a butted contact disposed above and extending from the first source or drain region to at least one of the first or second gate, a portion of the first gate spacer extending a distance into the butted contact to separate a first bottom surface of the butted contact from a second bottom surface of the butted contact.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Leo Hsu, Sheng-Liang Pan
  • Publication number: 20210400235
    Abstract: In one embodiment, a method includes establishing a video call between a plurality of client systems, sending, to a first client system of the plurality of client systems while maintaining the video call between the plurality of client systems, instructions for presenting a first content recommendation comprising one or more selected content items, wherein the first content recommendation comprises a prompt to share the selected content items with one or more second client systems of the plurality of client systems, receiving, from the first client system responsive to the prompt, a request to share the selected content items, and sending, to the one or more second client systems responsive to receiving the request and while maintaining the video call between the plurality of client systems, instructions for presenting the selected content items within the video call.
    Type: Application
    Filed: September 2, 2021
    Publication date: December 23, 2021
    Inventors: Sravani Kamisetty, Xiaolei Li, Yuan Chang, Ting Chen Leo Hsu
  • Publication number: 20210358813
    Abstract: A gate structure is formed over a substrate. The gate structure includes a gate electrode and a hard mask located over the gate electrode. The hard mask comprises a first dielectric material. A first interlayer dielectric (ILD) is formed over the gate structure. The first ILD comprises a second dielectric material different from the first dielectric material. A first via is formed in the first ILD. Sidewalls of the first via are surrounded by spacers that comprise the first dielectric material. A second ILD is formed over the first ILD. A via hole is formed in the second ILD. The via hole exposes the first via. A protective layer is formed in the via hole. A bottom segment of the protective layer is removed. Thereafter, an etching process is performed. A remaining segment of the protective layer prevents an etching of the spacers during the etching process.
    Type: Application
    Filed: July 28, 2021
    Publication date: November 18, 2021
    Inventors: Leo Hsu, Louis Lin
  • Patent number: 11159767
    Abstract: In one embodiment, a method includes establishing a video call between multiple client systems and determining user identifiers of users associated with the video call. Whether to provide content recommendations during the video call may then be determined based on a current context of that video call, and one or more content items to recommend may be selected based on the determined user identifiers. Finally, in response to determining to provide content recommendations during the video call, a first content recommendation with the selected content items may be sent to one or more of the client systems while maintaining the video call between those client systems.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: October 26, 2021
    Assignee: Facebook Technologies, LLC
    Inventors: Sravani Kamisetty, Xiaolei Li, Yuan Chang, Ting Chen Leo Hsu
  • Publication number: 20210314523
    Abstract: In one embodiment, a method includes establishing a video call between multiple client systems and determining user identifiers of users associated with the video call. Whether to provide content recommendations during the video call may then be determined based on a current context of that video call, and one or more content items to recommend may be selected based on the determined user identifiers. Finally, in response to determining to provide content recommendations during the video call, a first content recommendation with the selected content items may be sent to one or more of the client systems while maintaining the video call between those client systems.
    Type: Application
    Filed: April 7, 2020
    Publication date: October 7, 2021
    Inventors: Sravani Kamisetty, Xiaolei Li, Yuan Chang, Ting Chen Leo Hsu
  • Patent number: 11081397
    Abstract: A gate structure is formed over a substrate. The gate structure includes a gate electrode and a hard mask located over the gate electrode. The hard mask comprises a first dielectric material. A first interlayer dielectric (ILD) is formed over the gate structure. The first ILD comprises a second dielectric material different from the first dielectric material. A first via is formed in the first ILD. Sidewalls of the first via are surrounded by spacers that comprise the first dielectric material. A second ILD is formed over the first ILD. A via hole is formed in the second ILD. The via hole exposes the first via. A protective layer is formed in the via hole. A bottom segment of the protective layer is removed. Thereafter, an etching process is performed. A remaining segment of the protective layer prevents an etching of the spacers during the etching process.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Leo Hsu, Louis Lin
  • Publication number: 20200381298
    Abstract: A butted contact structure is provided. In one embodiment, a structure includes a first transistor on a substrate, the first transistor comprising a first source or drain region, a first gate, and a first gate spacer being disposed between the first gate and the first source or drain region. The structure includes a second transistor on the substrate, the second transistor comprising a second source or drain region, a second gate, and a second gate spacer being disposed between the second gate and the second source or drain region. The structure includes a butted contact disposed above and extending from the first source or drain region to at least one of the first or second gate, a portion of the first gate spacer extending a distance into the butted contact to separate a first bottom surface of the butted contact from a second bottom surface of the butted contact.
    Type: Application
    Filed: August 17, 2020
    Publication date: December 3, 2020
    Inventors: Leo Hsu, Sheng-Liang Pan
  • Patent number: 10755978
    Abstract: A butted contact structure is provided. In one embodiment, a structure includes a first transistor on a substrate, the first transistor comprising a first source or drain region, a first gate, and a first gate spacer being disposed between the first gate and the first source or drain region. The structure includes a second transistor on the substrate, the second transistor comprising a second source or drain region, a second gate, and a second gate spacer being disposed between the second gate and the second source or drain region. The structure includes a butted contact disposed above and extending from the first source or drain region to at least one of the first or second gate, a portion of the first gate spacer extending a distance into the butted contact to separate a first bottom surface of the butted contact from a second bottom surface of the butted contact.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Leo Hsu, Sheng-Liang Pan
  • Publication number: 20200090999
    Abstract: A butted contact structure is provided. In one embodiment, a structure includes a first transistor on a substrate, the first transistor comprising a first source or drain region, a first gate, and a first gate spacer being disposed between the first gate and the first source or drain region. The structure includes a second transistor on the substrate, the second transistor comprising a second source or drain region, a second gate, and a second gate spacer being disposed between the second gate and the second source or drain region. The structure includes a butted contact disposed above and extending from the first source or drain region to at least one of the first or second gate, a portion of the first gate spacer extending a distance into the butted contact to separate a first bottom surface of the butted contact from a second bottom surface of the butted contact.
    Type: Application
    Filed: November 22, 2019
    Publication date: March 19, 2020
    Inventors: Leo Hsu, Sheng-Liang Pan
  • Publication number: 20200043800
    Abstract: A gate structure is formed over a substrate. The gate structure includes a gate electrode and a hard mask located over the gate electrode. The hard mask comprises a first dielectric material. A first interlayer dielectric (ILD) is formed over the gate structure. The first ILD comprises a second dielectric material different from the first dielectric material. A first via is formed in the first ILD. Sidewalls of the first via are surrounded by spacers that comprise the first dielectric material. A second ILD is formed over the first ILD. A via hole is formed in the second ILD. The via hole exposes the first via. A protective layer is formed in the via hole. A bottom segment of the protective layer is removed. Thereafter, an etching process is performed. A remaining segment of the protective layer prevents an etching of the spacers during the etching process.
    Type: Application
    Filed: October 14, 2019
    Publication date: February 6, 2020
    Inventors: Leo Hsu, Louis Lin
  • Patent number: 10510600
    Abstract: A butted contact structure is provided. In one embodiment, a structure includes a first transistor on a substrate, the first transistor comprising a first source or drain region, a first gate, and a first gate spacer being disposed between the first gate and the first source or drain region. The structure includes a second transistor on the substrate, the second transistor comprising a second source or drain region, a second gate, and a second gate spacer being disposed between the second gate and the second source or drain region. The structure includes a butted contact disposed above and extending from the first source or drain region to at least one of the first or second gate, a portion of the first gate spacer extending a distance into the butted contact to separate a first bottom surface of the butted contact from a second bottom surface of the butted contact.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Leo Hsu, Sheng-Liang Pan
  • Patent number: 10446449
    Abstract: A gate structure is formed over a substrate. The gate structure includes a gate electrode and a hard mask located over the gate electrode. The hard mask comprises a first dielectric material. A first interlayer dielectric (ILD) is formed over the gate structure. The first ILD comprises a second dielectric material different from the first dielectric material. A first via is formed in the first ILD. Sidewalls of the first via are surrounded by spacers that comprise the first dielectric material. A second ILD is formed over the first ILD. A via hole is formed in the second ILD. The via hole exposes the first via. A protective layer is formed in the via hole. A bottom segment of the protective layer is removed. Thereafter, an etching process is performed. A remaining segment of the protective layer prevents an etching of the spacers during the etching process.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: October 15, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Leo Hsu, Louis Lin
  • Publication number: 20180308760
    Abstract: A gate structure is formed over a substrate. The gate structure includes a gate electrode and a hard mask located over the gate electrode. The hard mask comprises a first dielectric material. A first interlayer dielectric (ILD) is formed over the gate structure. The first ILD comprises a second dielectric material different from the first dielectric material. A first via is formed in the first ILD. Sidewalls of the first via are surrounded by spacers that comprise the first dielectric material. A second ILD is formed over the first ILD. A via hole is formed in the second ILD. The via hole exposes the first via. A protective layer is formed in the via hole. A bottom segment of the protective layer is removed. Thereafter, an etching process is performed. A remaining segment of the protective layer prevents an etching of the spacers during the etching process.
    Type: Application
    Filed: June 25, 2018
    Publication date: October 25, 2018
    Inventors: Leo Hsu, Louis Lin
  • Patent number: 10008416
    Abstract: A gate structure is formed over a substrate. The gate structure includes a gate electrode and a hard mask located over the gate electrode. The hard mask comprises a first dielectric material. A first interlayer dielectric (ILD) is formed over the gate structure. The first ILD comprises a second dielectric material different from the first dielectric material. A first via is formed in the first ILD. Sidewalls of the first via are surrounded by spacers that comprise the first dielectric material. A second ILD is formed over the first ILD. A via hole is formed in the second ILD. The via hole exposes the first via. A protective layer is formed in the via hole. A bottom segment of the protective layer is removed. Thereafter, an etching process is performed. A remaining segment of the protective layer prevents an etching of the spacers during the etching process.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: June 26, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Leo Hsu, Louis Lin
  • Publication number: 20180151445
    Abstract: A gate structure is formed over a substrate. The gate structure includes a gate electrode and a hard mask located over the gate electrode. The hard mask comprises a first dielectric material. A first interlayer dielectric (ILD) is formed over the gate structure. The first ILD comprises a second dielectric material different from the first dielectric material. A first via is formed in the first ILD. Sidewalls of the first via are surrounded by spacers that comprise the first dielectric material. A second ILD is formed over the first ILD. A via hole is formed in the second ILD. The via hole exposes the first via. A protective layer is formed in the via hole. A bottom segment of the protective layer is removed. Thereafter, an etching process is performed. A remaining segment of the protective layer prevents an etching of the spacers during the etching process.
    Type: Application
    Filed: November 30, 2016
    Publication date: May 31, 2018
    Inventors: Leo Hsu, Louis Lin