Patents by Inventor Leo J. Craft

Leo J. Craft has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data storage system using wafer-level packaging
    Patent number: 10964682
    Abstract: A data storage system is described that uses wafer-level packaging. In one embodiment an apparatus includes a silicon wafer, a plurality of memory cells formed directly on the wafer, an encapsulant formed over the memory cells, a plurality of wiring connections to connect the memory cells to an external interface, a memory controller, and an external interface.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: John G. Meyers, Leo J. Craft
  • DATA STORAGE SYSTEM USING WAFER-LEVEL PACKAGING
    Publication number: 20190172820
    Abstract: A data storage system is described that uses wafer-level packaging. In one embodiment an apparatus includes a silicon wafer, a plurality of memory cells formed directly on the wafer, an encapsulant formed over the memory cells, a plurality of wiring connections to connect the memory cells to an external interface, a memory controller, and an external interface.
    Type: Application
    Filed: September 30, 2016
    Publication date: June 6, 2019
    Inventors: John G. MEYERS, Leo J. CRAFT
  • Microelectronic assembly having second level interconnects including solder joints reinforced with crack arrester elements and method of forming same
    Patent number: 7750466
    Abstract: A microelectronic assembly and a method of forming the assembly. The microelectronic assembly includes a package having a package substrate having a die side and a carrier side, and substrate lands on the carrier side thereof; a microelectronic die mounted on the package substrate at the die side thereof; and an array of first level interconnects electrically coupling the die to the package substrate. The assembly further includes a carrier having a substrate side, the package being mounted on the carrier at the substrate side thereof; and an array of second level interconnects electrically coupling the package to the carrier, each of the second level interconnects including a solder joint connecting the substrate lands to the carrier lands, and a crack arrester element at least partially encompassed within the solder joint.
    Type: Grant
    Filed: September 7, 2007
    Date of Patent: July 6, 2010
    Assignee: Intel Corporation
    Inventors: Timothy P. Rothman, Leo J. Craft, Dong W. Kim
  • Microelectronic Assembly Having Second Level Interconnects Including Solder Joints Reinforced with Crack Arrester Elements and Method of Forming Same
    Publication number: 20090065943
    Abstract: A microelectronic assembly and a method of forming the assembly. The microelectronic assembly includes a package having a package substrate having a die side and a carrier side, and substrate lands on the carrier side thereof; a microelectronic die mounted on the package substrate at the die side thereof; and an array of first level interconnects electrically coupling the die to the package substrate. The assembly further includes a carrier having a substrate side, the package being mounted on the carrier at the substrate side thereof; and an array of second level interconnects electrically coupling the package to the carrier, each of the second level interconnects including a solder joint connecting the substrate lands to the carrier lands, and a crack arrester element at least partially encompassed within the solder joint.
    Type: Application
    Filed: September 7, 2007
    Publication date: March 12, 2009
    Inventors: Timothy P. Rothman, Leo J. Craft, Dong W. Kim