Patents by Inventor Leo Merilo
Leo Merilo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9281300Abstract: A semiconductor package includes a ball grid array (BGA) substrate having integrated metal layer circuitry, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the BGA substrate, and an application die attached to the IPD. A method of manufacturing a semiconductor package includes providing a BGA substrate having integrated metal layer circuitry, attaching a flip chip CSMP having a first IPD to the BGA substrate, and attaching an application die to the IPD.Type: GrantFiled: September 15, 2010Date of Patent: March 8, 2016Assignee: STATS ChipPAC, Ltd.Inventors: Leo A. Merilo, Emmanuel A. Espiritu, Dario S. Filoteo, Jr., Rachel L. Abinan
-
Patent number: 8395254Abstract: An integrated circuit package system includes providing a substrate having an integrated circuit, attaching a heatspreader having a force control protrusion on the substrate, and forming an encapsulant over the heatspreader and the integrated circuit.Type: GrantFiled: March 30, 2006Date of Patent: March 12, 2013Assignee: STATS Chippac Ltd.Inventors: Emmanuel Espiritu, Dario S. Filoteo, Jr., Leo A. Merilo, Philip Lyndon Cablao, Rachel Layda Abinan, Allan Ilagan
-
Patent number: 8138080Abstract: An integrated circuit package system is provided forming an integrated circuit die having a first bond pad provided thereon, forming an interconnect stack on a first external interconnect, and connecting the interconnect stack to the first bond pad.Type: GrantFiled: March 10, 2006Date of Patent: March 20, 2012Assignee: Stats Chippac Ltd.Inventors: Dario S. Filoteo, Jr., Leo A. Merilo, Philip Lyndon Cablao, Emmanuel Espiritu, Rachel Layda Abinan, Allan Ilagan
-
Patent number: 8097496Abstract: A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe having a lead, a first quad flat nonleaded package (QFN) connected to the lead, and a second quad flat nonleaded package invertly connected to a top surface of the first quad flat nonleaded package, wherein the second quad flat nonleaded package is wirebonded to the lead. A third embodiment of a semiconductor package includes a leadframe having a lead with a first level downset lead extension, a quad flat nonleaded package (QFN) connected to the first level downset lead extension, and a first wirebondable die attached to a top or bottom surface of the quad flat nonleaded package.Type: GrantFiled: February 10, 2010Date of Patent: January 17, 2012Assignee: STATS ChipPAC, Ltd.Inventors: Emmanuel A. Espiritu, Leo A. Merilo, Rachel L. Abinan, Dario S. Filoteo, Jr.
-
Patent number: 8097935Abstract: A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe having a lead, a first quad flat nonleaded package (QFN) connected to the lead, and a second quad flat nonleaded package invertly connected to a top surface of the first quad flat nonleaded package, wherein the second quad flat nonleaded package is wirebonded to the lead. A third embodiment of a semiconductor package includes a leadframe having a lead with a first level downset lead extension, a quad flat nonleaded package (QFN) connected to the first level downset lead extension, and a first wirebondable die attached to a top or bottom surface of the quad flat nonleaded package.Type: GrantFiled: February 10, 2010Date of Patent: January 17, 2012Assignee: STATS ChipPAC, Ltd.Inventors: Emmanuel A. Espiritu, Leo A. Merilo, Rachel L. Abinan, Dario S. Filoteo, Jr.
-
Patent number: 8026129Abstract: A stacked integrated circuit package system is provided forming a first stack layer having a first integrated circuit die on a first substrate, forming a second stack layer having a second integrated circuit die on a second substrate, and mechanically and electrically connecting a spacer layer having a first passive component between the second stack layer and the first stack layer.Type: GrantFiled: March 10, 2006Date of Patent: September 27, 2011Assignee: STATS ChipPAC Ltd.Inventors: Philip Lyndon Cablao, Dario S. Filoteo, Jr., Leo A. Merilo, Emmanuel Espiritu, Rachel Layda Abinan, Allan Ilagan
-
Publication number: 20110001240Abstract: A semiconductor package includes a ball grid array (BGA) substrate having integrated metal layer circuitry, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the BGA substrate, and an application die attached to the IPD. A method of manufacturing a semiconductor package includes providing a BGA substrate having integrated metal layer circuitry, attaching a flip chip CSMP having a first IPD to the BGA substrate, and attaching an application die to the IPD.Type: ApplicationFiled: September 15, 2010Publication date: January 6, 2011Applicant: STATS CHIPPAC, LTD.Inventors: Leo A. Merilo, Emmanuel A. Espiritu, Dario S. Filoteo, JR., Rachel L. Abinan
-
Patent number: 7786575Abstract: A stacked die semiconductor package includes a first integrated circuit chip, a first circuit tape coupled to the first integrated circuit chip, a second integrated circuit chip coupled to the first circuit tape, and at least one component coupled to the first circuit tape. The at least one component may include one or more passive components, one or more active components, or a combination of passive and active components. The stacked die semiconductor package can also include a second circuit tape coupled to the second integrated circuit chip and a third integrated circuit chip coupled to the second circuit tape. The stacked die semiconductor package can also include an encapsulant.Type: GrantFiled: December 4, 2009Date of Patent: August 31, 2010Assignee: STATS ChipPAC Ltd.Inventors: Philip Lyndon R. Cablao, Dario S. Filoteo, Jr., Emmanuel A. Espiritu, Leo A. Merilo
-
Publication number: 20100140761Abstract: A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe having a lead, a first quad flat nonleaded package (QFN) connected to the lead, and a second quad flat nonleaded package invertly connected to a top surface of the first quad flat nonleaded package, wherein the second quad flat nonleaded package is wirebonded to the lead. A third embodiment of a semiconductor package includes a leadframe having a lead with a first level downset lead extension, a quad flat nonleaded package (QFN) connected to the first level downset lead extension, and a first wirebondable die attached to a top or bottom surface of the quad flat nonleaded package.Type: ApplicationFiled: February 10, 2010Publication date: June 10, 2010Applicant: STATS CHIPPAC, LTD.Inventors: Emmanuel A. Espiritu, Leo A. Merilo, Rachel L. Abinan, Dario S. Filoteo, JR.
-
Publication number: 20100144100Abstract: A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe having a lead, a first quad flat nonleaded package (QFN) connected to the lead, and a second quad flat nonleaded package invertly connected to a top surface of the first quad flat nonleaded package, wherein the second quad flat nonleaded package is wirebonded to the lead. A third embodiment of a semiconductor package includes a leadframe having a lead with a first level downset lead extension, a quad flat nonleaded package (QFN) connected to the first level downset lead extension, and a first wirebondable die attached to a top or bottom surface of the quad flat nonleaded package.Type: ApplicationFiled: February 10, 2010Publication date: June 10, 2010Applicant: STATS CHIPPAC, LTD.Inventors: Emmanuel A. Espiritu, Leo A. Merilo, Rachel L. Abinan, Dario S. Filoteo, JR.
-
Publication number: 20100078794Abstract: A stacked die semiconductor package includes a first integrated circuit chip, a first circuit tape coupled to the first integrated circuit chip, a second integrated circuit chip coupled to the first circuit tape, and at least one component coupled to the first circuit tape. The at least one component may include one or more passive components, one or more active components, or a combination of passive and active components. The stacked die semiconductor package can also include a second circuit tape coupled to the second integrated circuit chip and a third integrated circuit chip coupled to the second circuit tape. The stacked die semiconductor package can also include an encapsulant.Type: ApplicationFiled: December 4, 2009Publication date: April 1, 2010Inventors: Philip Lyndon R. Cablao, Dario S. Filoteo, JR., Emmanuel A. Espiritu, Leo A. Merilo
-
Patent number: 7687892Abstract: A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe having a lead, a first quad flat nonleaded package (QFN) connected to the lead, and a second quad flat nonleaded package invertly connected to a top surface of the first quad flat nonleaded package, wherein the second quad flat nonleaded package is wirebonded to the lead. A third embodiment of a semiconductor package includes a leadframe having a lead with a first level downset lead extension, a quad flat nonleaded package (QFN) connected to the first level downset lead extension, and a first wirebondable die attached to a top or bottom surface of the quad flat nonleaded package.Type: GrantFiled: August 8, 2006Date of Patent: March 30, 2010Assignee: STATS ChipPAC, Ltd.Inventors: Emmanuel A. Espiritu, Leo A. Merilo, Rachel L. Abinan, Dario S. Filoteo, Jr.
-
Patent number: 7659608Abstract: A stacked die semiconductor package includes a first integrated circuit chip, a first circuit tape coupled to the first integrated circuit chip, a second integrated circuit chip coupled to the first circuit tape, and at least one component coupled to the first circuit tape. The at least one component may include one or more passive components, one or more active components, or a combination of passive and active components. The stacked die semiconductor package can also include a second circuit tape coupled to the second integrated circuit chip and a third integrated circuit chip coupled to the second circuit tape. The stacked die semiconductor package can also include an encapsulant.Type: GrantFiled: September 15, 2006Date of Patent: February 9, 2010Assignee: Stats Chippac Ltd.Inventors: Philip Lyndon R. Cablao, Dario S. Filoteo, Jr., Emmanuel A. Espiritu, Leo A. Merilo
-
Patent number: 7439620Abstract: An integrated circuit package-in-package system is provided including forming an external interconnect having an upper portion and a lower portion; forming a packaged device; mounting an active device over the packaged device; connecting the active device to the packaged device and the upper portion; and molding the packaged device, the active device, and the upper portion.Type: GrantFiled: August 4, 2006Date of Patent: October 21, 2008Assignee: Stats Chippac Ltd.Inventors: Leo A. Merilo, Emmanuel Espiritu, Philip Lyndon Cablao, Dario S. Filoteo, Jr.
-
Publication number: 20080067658Abstract: A stacked die semiconductor package comprises a first integrated circuit chip, a first circuit tape coupled to the first integrated circuit chip, a second integrated circuit chip coupled to the first circuit tape, and at least one component coupled to the first circuit tape. The at least one component may include one or more passive components, one or more active components, or a combination of passive and active components. The stacked die semiconductor package can also comprise a second circuit tape coupled to the second integrated circuit chip and a third integrated circuit chip coupled to the second circuit tape. The stacked die semiconductor package can also comprise an encapsulant.Type: ApplicationFiled: September 15, 2006Publication date: March 20, 2008Inventors: Philip Lyndon R. Cablao, Dario S. Filoteo, Emmanuel A. Espiritu, Leo A. Merilo
-
Publication number: 20080042265Abstract: A semiconductor package includes a ball grid array (BGA) substrate having integrated metal layer circuitry, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the ball grid array (BGA) substrate, and an application die attached to the integrated passive device (IPD). A method of manufacturing a semiconductor package includes providing a ball grid array (BGA) substrate having integrated metal layer circuitry, attaching a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD) to the ball grid array (BGA) substrate, and attaching an application die to the integrated passive device (IPD).Type: ApplicationFiled: August 15, 2006Publication date: February 21, 2008Inventors: Leo A. Merilo, Emmanuel A. Espiritu, Dario S. Filoteo, Rachel L. Abinan
-
Publication number: 20080036051Abstract: A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe having a lead, a first quad flat nonleaded package (QFN) connected to the lead, and a second quad flat nonleaded package invertly connected to a top surface of the first quad flat nonleaded package, wherein the second quad flat nonleaded package is wirebonded to the lead. A third embodiment of a semiconductor package includes a leadframe having a lead with a first level downset lead extension, a quad flat nonleaded package (QFN) connected to the first level downset lead extension, and a first wirebondable die attached to a top or bottom surface of the quad flat nonleaded package.Type: ApplicationFiled: August 8, 2006Publication date: February 14, 2008Inventors: Emmanuel A. Espiritu, Leo A. Merilo, Rachel L. Abinan, Dario S. Filoteo
-
Publication number: 20080029905Abstract: An integrated circuit package-in-package system is provided including forming an external interconnect having an upper portion and a lower portion; forming a packaged device; mounting an active device over the packaged device; connecting the active device to the packaged device and the upper portion; and molding the packaged device, the active device, and the upper portion.Type: ApplicationFiled: August 4, 2006Publication date: February 7, 2008Applicant: STATS CHIPPAC LTD.Inventors: Leo A. Merilo, Emmanuel Espiritu, Philip Lyndon Cablao, Dario S. Filoteo
-
Publication number: 20070235859Abstract: An integrated circuit package system includes providing a substrate having an integrated circuit, attaching a heatspreader having a force control protrusion on the substrate, and forming an encapsulant over the heatspreader and the integrated circuit.Type: ApplicationFiled: March 30, 2006Publication date: October 11, 2007Applicant: STATS ChipPAC Ltd.Inventors: Emmanuel Espiritu, Dario Filoteo, Leo Merilo, Philip Cablao, Rachel Abinan, Allan Ilagan
-
Publication number: 20070210432Abstract: A stacked integrated circuit package system is provided forming a first stack layer having a first integrated circuit die on a first substrate, forming a second stack layer having a second integrated circuit die on a second substrate, and mechanically and electrically connecting a spacer layer having a first passive component between the second stack layer and the first stack layer.Type: ApplicationFiled: March 10, 2006Publication date: September 13, 2007Applicant: STATS CHIPPAC LTD.Inventors: Philip Cablao, Dario Filoteo, Leo Merilo, Emmanuel Espiritu, Rachel Abinan, Allan Ilagan