Abstract: Vertical PNP and the NPN transistors, each having a gain-bandwidth product greater than 1 GHz are formed in dielectrically isolated regions in polysilicon substrate. The substrate may include additionally dielectrically isolated regions for other devices such as thin oxide capacitors. On one surface of the substrate between the respective device regions a thick field insulator (oxide) layer is formed to minimize parasitics between interconnects and the substrate. Atop this thick field oxide one or more thin film resistors may be formed. Contacts and interconnect metallization for the bipolar devices, capacitors and thin film resistors are preferably made of silicon-doped-aluminum. In the course of manufacture of the PNP and NPN devices like conductivity type regions are formed simultaneously so as to control the parameters of each device. The relatively high f.sub.

Abstract: Vertical PNP and the NPN transistors, each having a gain-bandwidth product greater than 1 GHz are formed in dielectrically isolated regions in a polysilicon substrate. The substrate may include additional dielectrically isolated regions for other devices such as thin oxide capacitors. On one surface of the substrate between the respective device regions a thick field insulator (oxide) layer is formed to minimize parasitics between interconnects and the substrate. Atop this thick field oxide one or more thin film resistors may be formed. Contacts and interconnect metallization for the bipolar devices, capacitors and thin film resistors are preferably made of silicon-doped-aluminum. In the course of manufacture of the PNP and NPN devices like conductivity type regions are formed simultaneously so as to control the parameters of each device. The relatively high f.sub.

Abstract: Specific impurity concentration regions are used for the simultaneous formation of CMOS devices and complementary bipolar transistors to produce high voltage, high performance bipolar transistors. The last diffusion step for shallow P.sup.+ and N.sup.+ emitter regions and contact regions is performed without a separate diffusion cycle. The formation of the gate oxide at a relatively low temperature is followed immediately by the formation of an undoped polysilicon gate layer. The polysilicon gate layer is doped to a reasonable resistance and also forms a first level interconnect. Phosphorous doped CVD silicon oxide is formed thereover and the top surface is treated with additional phosphorous to produce tapered contact apertures therethrough when etched. A layer of metal is applied and delineated to form contacts to the substrate regions and to form the second level of interconnects.

Abstract: A Schottky barrier diode is formed in a low impurity concentration N-type substrate by ion implanting N-type impurities to form a deep region having increased impurity surface concentration of at least 10.sup.16 carriers per cubic centimeters, forming P-type guard ring in the deep N-type region and forming an N.sup.+ contact region in the deep N-type region. NPN transistors can be fabricated in the original low impurity substrate or in an ion implanted substrate region having a lower breakdown voltage. Schottky clamped NPN transistors formed in the low impurity substrate include ion implanted regions interior to a base ring and extending down into a buried N.sup.+ collector region as does an ion implanted surface collector contact region having an N.sup.+ contact area.