Patents by Inventor Leo van Gemert

Leo van Gemert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11011446
    Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside. The semiconductor device also includes at least one metal layer extending across the backside of the substrate. A peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface. This can prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: May 18, 2021
    Assignee: NEXPERIA B.V.
    Inventors: Tonny Kamphuis, Leo van Gemert, Hans van Rijckevorsel, Sascha Moeller, Hartmut Buenning, Steffen Holland, Y Kuang Huang
  • Publication number: 20210134612
    Abstract: A method of forming an assembly is provided. The method includes attaching a packaged semiconductor device to a substrate. An isolation structure is formed and located between the packaged semiconductor device and the substrate. An underfill material is dispensed between the packaged semiconductor device and the substrate. The isolation structure prevents the underfill material from contacting a first conductive connection formed between the packaged semiconductor device and the substrate.
    Type: Application
    Filed: October 31, 2019
    Publication date: May 6, 2021
    Inventors: Leo van Gemert, Peter Joseph Hubert Drummen
  • Publication number: 20210066209
    Abstract: A structure is provided that reduces the stress generated in a semiconductor device package during cooling subsequent to solder reflow operations for coupling semiconductor devices to a printed circuit board (PCB). Stress reduction is provided by coupling solder lands to metal-layer structures using traces on the PCB that are oriented approximately perpendicular to lines from an expansion neutral point associated with the package. In many cases, especially where the distribution of solder lands of the semiconductor device package are uniform, the expansion neutral point is in the center of the semiconductor device package. PCB traces having such an orientation experience reduced stress due to thermal-induced expansion and contraction as compared to traces having an orientation along a line to the expansion neutral point.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Applicant: NXP B.V.
    Inventors: Leo van Gemert, Jeroen Johannes Maria Zaal, Michiel van Soestbergen, Romuald Olivier Nicolas Roucou
  • Patent number: 10825789
    Abstract: One embodiment of a packaged semiconductor device includes: a redistributed layer (RDL) structure formed over an active side of a semiconductor die embedded in mold compound, the RDL structure includes a plurality of solder ball pads that in turn includes: a set of first solder ball pads located on a front side of the packaged semiconductor device within a footprint of the semiconductor die, and a set of second solder ball pads located on the front side of the packaged semiconductor device outside of the footprint of the semiconductor die, each first solder ball pad includes a first center portion having a first diameter measured between opposite outer edges of the first center portion, each second solder ball pad includes a second center portion having a second diameter measured between opposite outer edges of the second center portion, and the first diameter is smaller than the second diameter.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: November 3, 2020
    Assignee: NXP B.V.
    Inventors: Leo Van Gemert, Adrianus Buijsman, Jeroen Johannes Maria Zaal, Michiel Van Soestbergen, Peter Joseph Hubert Drummen
  • Patent number: 10615134
    Abstract: An integrated circuit package is described comprising an integrated circuit die and an antenna structure coupled to the integrated circuit die and comprising a stacked arrangement of metal and dielectric layers, wherein a first metal layer includes a planar antenna and at least one further metal layer comprises an artificial dielectric layer. The integrated circuit package may improve the directionality of the antenna and reduces the sensitivity of the antenna to the printed circuit board on which the integrated circuit package is mounted.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: April 7, 2020
    Assignee: NXP B.V.
    Inventors: Maristella Spella, Waqas Hassan Syed, Daniele Cavallo, Mingda Huang, Leo Van Gemert
  • Patent number: 10613136
    Abstract: An apparatus comprising: a substrate; an integrated circuit region formed in the substrate; a seal ring disposed in the substrate to form a ring around the integrated circuit region, the seal ring configured to provide for protection against one or more of moisture ingress and ion ingress to the integrated circuit region and crack propagation through the substrate; and a defect sensor comprising a conductive track formed of at least one conductive layer in the substrate, the conductive track disposed outwardly of the seal ring and arranged to at least partially surround the integrated circuit region and seal ring, the conductive track having a first end terminal and a second end terminal to receive a detection signal therebetween to pass through the conductive track to detect a break in the conductive track and thereby a defect in the substrate.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: April 7, 2020
    Assignee: NXP B.V.
    Inventors: Leo Van Gemert, Peter Drummen
  • Patent number: 10315821
    Abstract: One example discloses a component carrier, including: a cavity; wherein the cavity includes a set of cavity registration features configured to engage with a set of component registration features on a component; and wherein the cavity registration features are within the cavity.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: June 11, 2019
    Assignee: NXP B.V.
    Inventors: Jeroen Johannes Maria Zaal, Roelf Anco Jacob Groenhuis, Leo van Gemert, Caroline Catharina Maria Beelen-Hendrikx
  • Publication number: 20190011496
    Abstract: An apparatus comprising: a substrate; an integrated circuit region formed in the substrate; a seal ring disposed in the substrate to form a ring around the integrated circuit region, the seal ring configured to provide for protection against one or more of moisture ingress and ion ingress to the integrated circuit region and crack propagation through the substrate; and a defect sensor comprising a conductive track formed of at least one conductive layer in the substrate, the conductive track disposed outwardly of the seal ring and arranged to at least partially surround the integrated circuit region and seal ring, the conductive track having a first end terminal and a second end terminal to receive a detection signal therebetween to pass through the conductive track to detect a break in the conductive track and thereby a defect in the substrate.
    Type: Application
    Filed: July 9, 2018
    Publication date: January 10, 2019
    Inventors: Leo VAN GEMERT, Peter DRUMMEN
  • Patent number: 10109564
    Abstract: This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity formed therein; forming electrical contacts at a base portion and sidewalls portions of the cavity; placing a semiconductor die in the base of the cavity; connecting bond pads of the semiconductor die to the electrical contacts; encapsulating the semiconductor die; and removing the carrier to expose the electrical contacts, such that the electrical contacts are arranged directly on the encapsulation material.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: October 23, 2018
    Assignee: NXP B.V.
    Inventors: Roelf Groenhuis, Leo Van Gemert, Tonny Kamphuis, Jan Gulpen
  • Publication number: 20180233465
    Abstract: An integrated circuit package is described comprising an integrated circuit die and an antenna structure coupled to the integrated circuit die and comprising a stacked arrangement of metal and dielectric layers, wherein a first metal layer includes a planar antenna and at least one further metal layer comprises an artificial dielectric layer. The integrated circuit package may improve the directionality of the antenna and reduces the sensitivity of the antenna to the printed circuit board on which the integrated circuit package is mounted.
    Type: Application
    Filed: January 15, 2018
    Publication date: August 16, 2018
    Inventors: Maristella SPELLA, Waqas Hassan SYED, Daniele CAVALLO, Mingda HUANG, Leo VAN GEMERT
  • Publication number: 20180134473
    Abstract: One example discloses a component carrier, including: a cavity; wherein the cavity includes a set of cavity registration features configured to engage with a set of component registration features on a component; and wherein the cavity registration features are within the cavity.
    Type: Application
    Filed: November 15, 2016
    Publication date: May 17, 2018
    Inventors: Jeroen Johannes Maria Zaal, Roelf Anco Jacob Groenhuis, Leo van Gemert, Caroline Catharina Maria Beelen-Hendrikx
  • Publication number: 20170372988
    Abstract: This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity formed therein; forming electrical contacts at a base portion and sidewalls portions of the cavity; placing a semiconductor die in the base of the cavity; connecting bond pads of the semiconductor die to the electrical contacts; encapsulating the semiconductor die; and removing the carrier to expose the electrical contacts, such that the electrical contacts are arranged directly on the encapsulation material.
    Type: Application
    Filed: February 13, 2017
    Publication date: December 28, 2017
    Inventors: ROELF GROENHUIS, LEO VAN GEMERT, TONNY KAMPHUIS, JAN GULPEN
  • Publication number: 20170148697
    Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside. The semiconductor device also includes at least one metal layer extending across the backside of the substrate. A peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface. This can prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier.
    Type: Application
    Filed: November 3, 2016
    Publication date: May 25, 2017
    Inventors: Tonny Kamphuis, Leo van Gemert, Hans van Rijckevorsel, Sascha Moeller, Hartmut Buenning, Steffen Holland, Y Kuang Huang
  • Patent number: 8679963
    Abstract: A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: March 25, 2014
    Assignee: NXP B.V.
    Inventors: Jan Gulpen, Tonny Kamphuis, Pieter Hochstenbach, Leo Van Gemert, Eric Van Grunsven, Marc De Samber
  • Publication number: 20130273731
    Abstract: A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads.
    Type: Application
    Filed: June 12, 2013
    Publication date: October 17, 2013
    Inventors: Jan GULPEN, Tonny KAMPHUIS, Pieter HOCHSTENBACH, Leo VAN GEMERT, Eric Van GRUNSVEN, Marc De SAMBER
  • Patent number: 8482136
    Abstract: A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: July 9, 2013
    Assignee: NXP B.V.
    Inventors: Jan Gulpen, Tonny Kamphuis, Pieter Hochstenbach, Leo van Gemert, Eric van Grunsven, Marc de Samber
  • Publication number: 20110156237
    Abstract: A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads.
    Type: Application
    Filed: December 29, 2009
    Publication date: June 30, 2011
    Applicant: NXP B.V.
    Inventors: Jan Gulpen, Tonny Kamphuis, Pieter Hochstenbach, Leo van Gemert, Eric van Grunsven, Marc de Samber