Abstract: A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.

Abstract: A noise margin self-diagnostic receiver circuit has been developed. The self-diagnostic circuit includes one comparator for comparing the signal voltage to a high reference voltage, a second comparator for comparing the signal voltage to a low reference voltage, and a logic circuit that activates an alarm if a noise error is detected. The circuit analyzes the data from the comparators and determines if a noise error has occurred dependent on being clocked by one or both of an output from the comparator comparing the signal voltage to the high reference voltage and an output from the comparator comparing the signal voltage to the low reference voltage.

Abstract: A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.

Abstract: A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.

Abstract: A method and apparatus for operating a source synchronous receiver. In one embodiment, a source synchronous receiver may include a clock receiver comprising a clock detector and a clock signal buffer. The clock detector may be configured to detect a first clock signal and assert a clock detect signal responsive to detecting the first clock signal. The clock buffer may receive the first clock signal and produce a second clock signal, which may be driven to a digital locked loop (DLL) circuit, where the second clock signal is regenerated and driven to a data buffer of the source synchronous receiver. The clock detect signal may be received by a clock verification circuit. The clock verification circuit may be configured to initiate a reset of the source synchronous receiver upon a failure to receive the clock detect signal.

Abstract: A source synchronous test methodology and apparatus. In one embodiment, an integrated circuit (IC) configured for source synchronous I/O transactions may be a device under test (DUT) and may be mounted to a load board for testing. The load board may be electrically coupled to a test system. The test system may shift first test data into a first IC on the load board. The first chip may then transmit the first test data through a source synchronous line, or a source synchronous link having a plurality of lines, to a second IC. Second test data produced responsive to the source synchronous transmission is then shifted from the second IC to the tester. The second test data is then analyzed. The analysis may comprise comparing the second data to expected data, and/or may also comprise analyzing the second data with respect to an eye window.

Abstract: One embodiment of the present invention provides a system for detecting a valid clock signal at a clock receiver. The system operates by receiving a clock signal at the clock receiver, and directing the clock signal into a control input of a voltage-controlled variable resistor. Next, the system uses the voltage-controlled variable resistor to control a first current. A current mirror is then employed to create a second current from the first current. This second current passes through a resistor to produce a control voltage, which is amplified to produce a validity signal indicating whether or not the clock signal is valid. In one embodiment of the present invention, the system additionally uses at least one capacitor to filter out periodic fluctuations in the validity signal.

Abstract: A source synchronous test methodology and apparatus. In one embodiment, an integrated circuit (IC) configured for source synchronous I/O transactions may be a device under test (DUT) and may be mounted to a load board for testing. The load board may be electrically coupled to a test system. The test system may shift first test data into a first IC on the load board. The first chip may then transmit the first test data through a source synchronous line, or a source synchronous link having a plurality of lines, to a second IC. Second test data produced responsive to the source synchronous transmission is then shifted from the second IC to the tester. The second test data is then analyzed. The analysis may comprise comparing the second data to expected data, and/or may also comprise analyzing the second data with respect to an eye window.

Abstract: An on-chip DC voltage generator providing a marginable reference voltage signal is described. The present invention is a CMOS-based integrated circuit that generates a marginable reference voltage level. The present invention provides a process insensitive reference voltage signal and may be configured so as to generate a ground-bounce-noise free signal.

Abstract: A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.

Abstract: An on-chip DC voltage generator providing a marginable reference voltage signal is described. The present invention is a CMOS-based integrated circuit that generates a marginable reference voltage level. The present invention provides a process insensitive reference voltage signal and may be configured so as to generate a ground-bounce-noise free signal.

Abstract: A method and circuitry for pre-emphasizing transmitted logic signals. The method and circuitry may be applied to single-ended center-taped terminated I/O lines. In one embodiment, a driver circuit may be configured for monitoring the logic values (i.e. logic 0, logic 1, or logic low, logic high) of signals transmitted by the driver circuit. The driver circuit may compare the logic value of a next logic signal to be transmitted with a first previously transmitted signal and a second previously transmitted signal. Pre-emphasis of the next logic signal may occur based on the logic value of the next logic signal to be transmitted as well as the logic values of the first and second logic signals. If the first and second logic signals have the same logic value, and the next logic signal has a different value, the next logic value may be pre-emphasized.

Abstract: A system and method for providing redundant, synchronized clocks in a computer system. Upon a failure of a master clock signal, the system switches over to a slave clock signal synchronized with the master clock signal. Switching logic is coupled to receive a first clock signal and a second clock signal. The switching logic selects either the first clock signal or the second clock signal as a local clock signal. The switching logic further monitors the first clock signal for a failure. If a failure is monitored, the switching logic accepts the second clock signal as the local clock signal in place of the first clock signal. One or more clock local loads operate according to the local clock signal. The switching logic may control the input to a phase locked loop (PLL) that provides the local clock signal to the local clock loads. The method includes a PLL synchronizing an output clock signal with the master clock signal. The output clock signal is used by at least one local clock load for timing.

Abstract: A process tracking reference voltage generator has been developed for an input/output system. The voltage generator includes a driver component that transmits an output signal to a receiver component. The receiver component generates a reference voltage in relation to the output signal as it varies with changing system operating conditions.

Abstract: A method and circuitry for pre-emphasizing transmitted logic signals. The method and circuitry may be applied to single-ended center-taped terminated I/O lines. In one embodiment, a driver circuit may be configured for monitoring the logic values (i.e. logic 0, logic 1, or logic low, logic high) of signals transmitted by the driver circuit. The driver circuit may compare the logic value of a next logic signal to be transmitted with a first previously transmitted signal and a second previously transmitted signal. Pre-emphasis of the next logic signal may occur based on the logic value of the next logic signal to be transmitted as well as the logic values of the first and second logic signals. If the first and second logic signals have the same logic value, and the next logic signal has a different value, the next logic value may be pre-emphasized.

Abstract: A digital communication system is presented including at least one transmission line coupled between a first and second communication devices and used to convey binary data from the first communication device to the second communication device. A termination resistor and one end of the transmission line are coupled to an input node of the second communication device. An electrical voltage level existing at the input node of the second communication device may be substantially dependent upon an amount of electrical current flowing through the termination resistor. The termination resistor may have a value substantially equal to a characteristic impedance of the transmission line such that signal reflections and distortion occurring within the transmission line are substantially reduced. Three or more different voltage levels may be present upon the transmission line dependent upon the binary data.

Abstract: A method and apparatus for operating a source synchronous receiver. In one embodiment, a source synchronous receiver may include a clock receiver comprising a clock detector and a clock signal buffer. The clock detector may be configured to detect a first clock signal and assert a clock detect signal responsive to detecting the first clock signal. The clock buffer may receive the first clock signal and produce a second clock signal, which may be driven to a digital locked loop (DLL) circuit, where the second clock signal is regenerated and driven to a data buffer of the source synchronous receiver. The clock detect signal may be received by a clock verification circuit. The clock verification circuit may be configured to initiate a reset of the source synchronous receiver upon a failure to receive the clock detect signal.

Abstract: One embodiment of the present invention provides a system for detecting a valid clock signal at a clock receiver. The system operates by receiving a clock signal at the clock receiver, and directing the clock signal into a control input of a voltage-controlled variable resistor. Next, the system uses the voltage-controlled variable resistor to control a first current. A current mirror is then employed to create a second current from the first current. This second current passes through a resistor to produce a control voltage, which is amplified to produce a validity signal indicating whether or not the clock signal is valid. In one embodiment of the present invention, the system additionally uses at least one capacitor to filter out periodic fluctuations in the validity signal.

Abstract: A system and method of reducing wire-or glitch to improve bus speeds. In a system that supports wire-or functions, the rise time of the wave created by the off-going driver is controlled. The off-going wave is forced to climb gradually such that one propagation delay of the loaded bus later, it is only marginally above a high threshold voltage. The fall time of the wave created by an on-going driver is minimized such that a strong negative going voltage propagates down the bus. This strong negative going voltage drags a composite wave on the bus (i.e. the combination of the waves of the on-going driver and the off-going driver) back below a low threshold voltage approximately one propagation delay after the switching occurs.

Abstract: An apparatus for dynamic termination logic of bi-directional data buses and methods of operating the same result in bi-directional data buses with improved data transfer performance. The bi-directional data bus for wire-or data transfers comprises a first end-driver coupled to a first end of the data bus configured to drive the first end of the data bus with a first signal. The second end-driver coupled to the second end of the data bus is configured to dynamically terminate the first signal from the first end-driver.