Abstract: A level converts circuit converting a digital input signal varying between a first (VSS) and a second (VDD1) voltage level to a digital output signal varying between the first (VSS) and a third voltage. (VDD2) the local conversion circuit includes between first (VDD2) and second (VSS) poles of a DC supply source a series connection of a load impedance (P2/P3/N3) and the main paths of a first transistor (N2) and of a second transistor (N1), to a control electrode of which the input signal is applied. The first and second transistor are of a same first conductivity type. A third transistor (P1) of a second conductivity type is connected in parallel with the second transistor (N1). A control electrode of the third (P1) and first (N2) transistors are biased by a constant DC bias voltage (VBIAS1A/VBIAS1B), and a junction point of the load impedance (P2/P3/N3) and the series connection being an output terminal (OUT) of the level conversion circuit.

Abstract: The synchronization method realizes synchronization of a digital input data signal with a digital clock signal with which the data signal is rate synchronous. The method consists in sampling the input signal, grouping these samples in successive sets of a plurality of successive ones of the samples, detecting in each of the sets possible value transitions of the samples, determining for each current transition in a set the theoretical position thereof in a corresponding set assumed to be obtained by sampling a nominal data signal which is the input data signal but with pulses having a width equal to the width of the clock signal period, and using the latter theoretical position and the end value of the transition to generate the synchronized input data signal.

Abstract: A synchronizing circuit to synchronize a digital input signal (DIN) with a clock signal (CK1) includes a detection circuit (DC) which checks if a present (SA) sample of a clock signal (CK3) being synchronized with the digital input signal, is equal to the previous (SB) sample, both samples being taken at an interval equal to the period (T) of the clock signal synchronized with the output signal. When the samples differ, the detection circuit generates a phase adjustment signal (CLR), which triggers a phase adjustment circuit (PAC) to ensure a return to synchronism by phase shifting the signal (ES) controlling the sampling of the digital input signal.

Abstract: A circuit to find the first bit 0 or 1 in an m-bit input word from a start bit onwards, the positions of these bits being defined by an n-bit code. It includes a crosspoint matrix of m (4) rows and n (2) columns, each crosspoint including a change-over contact (ABC), with a make contact (AB) and a break contact (AC), and another make contact (AD). The rows of change-over contacts (ABC) are controlled by respective bits of the m-bit word and the break contacts (AC) of the change-over contacts (ABC) of each row are coupled to respective bits of the n-bit code identifying the bit of the m-bit word respectively controlling these break contacts. Furthermore, the make contacts (AB) of the change-over contacts (ABC) of a same column are connected in a closed loop, while the other make contacts (AD) of a same column are connected in a parallel to a same output terminal (IA, IB), the rows of these other make contacts being controlled by a single-row selection circuit (TR).