Abstract: An ALU having improved propagate and generate signal section as well as carry and sum logic section to decrease the propagation delays. The propagate and generate signal section is specifically designed to be used with a dual ported RAM such that transition of the precharged RAM outputs to the desired outputs are used to trigger the logic. Latches, which are an integral part of the output of the propagate and generate signal section and are latched by the high/low transition of the output and reset by precharge signal, are used in combination with a special control sequence of the logic select of the propagate and generate section to isolate the latch and output such that one of the buses though the ALU may be used as a bidirectional bus so that the ALU may write back into the RAM without intermediate registers or latches.