Abstract: A technique for improving performance of a cache is provided. The technique involves maintaining indicators of whether cache entries are dirty in a random access memory (“RAM”) that has a lower latency to a cache controller than the cache memory that stores the cache entries. When a request to invalidate one or more cache entries is received by the cache controller, the cache controller checks the RAM to determine whether any cache entries are dirty and thus should be written out to a backing store. Using the RAM removes the need to check the actual cache memory for whether cache entries are dirty, which reduces the latency associated with performing such checks and thus with performing cache invalidations.

Abstract: A technique for scheduling processing tasks having different latencies is provided. The technique involves identifying one or more available requests in a request queue, where each request queue corresponds to a different latency. A request arbiter examines a shift register to determine whether there is an available slot for the one or more requests. A slot is available for a request if there is a slot that is a number of slots from the end of the shift register equal to the number of cycles the request takes to complete processing in a corresponding processing pipeline. If a slot is available, the request is scheduled for execution and the slot is marked as being occupied. If a slot is not available, the request is not scheduled for execution on the current cycle. On transitioning to a new cycle, the shift register is shifted towards its end and the technique repeats.

Abstract: A technique for prefetching data for a cache is provided. The technique includes detecting access to a data block. In response to the detection, a prefetch block generates proposed blocks for prefetch. The prefetch block also examines prefetch tracking data to determine whether a prefetch group including the proposed blocks is marked as already having been prefetched. If the group has been marked as already having been prefetched, then then prefetch block does not prefetch that data, thereby avoiding traffic between the prefetch block and the cache memory. Using this technique, unnecessary requests to prefetch data into the cache memory are avoided.

Abstract: A technique for improving performance of a data compression system is provided. The technique is applicable to compressed data sets that include compression blocks. Each compression block may be either compressed or uncompressed. Metadata indicating whether compression blocks are actually compressed or not is stored. If compression blocks are not compressed, then a read-decompress-modify-compress-write pipeline is bypassed. Instead, a compression unit writes the data specified by the partial request into the compression block, without reading, decompressing, modifying, recompressing, and writing the data, resulting in a much faster operation.

Abstract: A technique for prefetching data for a cache is provided. The technique includes detecting access to a data block. In response to the detection, a prefetch block generates proposed blocks for prefetch. The prefetch block also examines prefetch tracking data to determine whether a prefetch group including the proposed blocks is marked as already having been prefetched. If the group has been marked as already having been prefetched, then prefetch block does not prefetch that data, thereby avoiding traffic between the prefetch block and the cache memory. Using this technique, unnecessary requests to prefetch data into the cache memory are avoided.

Abstract: A technique for improving performance of a cache is provided. The technique involves maintaining indicators of whether cache entries are dirty in a random access memory (“RAM”) that has a lower latency to a cache controller than the cache memory that stores the cache entries. When a request to invalidate one or more cache entries is received by the cache controller, the cache controller checks the RAM to determine whether any cache entries are dirty and thus should be written out to a backing store. Using the RAM removes the need to check the actual cache memory for whether cache entries are dirty, which reduces the latency associated with performing such checks and thus with performing cache invalidations.

Abstract: A technique for scheduling processing tasks having different latencies is provided. The technique involves identifying one or more available requests in a request queue, where each request queue corresponds to a different latency. A request arbiter examines a shift register to determine whether there is an available slot for the one or more requests. A slot is available for a request if there is a slot that is a number of slots from the end of the shift register equal to the number of cycles the request takes to complete processing in a corresponding processing pipeline. If a slot is available, the request is scheduled for execution and the slot is marked as being occupied. If a slot is not available, the request is not scheduled for execution on the current cycle. On transitioning to a new cycle, the shift register is shifted towards its end and the technique repeats.

Abstract: A method is provided to manufacture a coated substrate, such as an optical fiber, without undesirable point lumps. The method filters a coating composition while controlling the filtering temperature, pressure drop across a filtering assembly, and filter pore size to achieve a resulting filtration factor not greater than 250,000 s?1. The filtration factor is a function of filtering temperature and pressure drop across the filtering assembly. Typically, the coating composition is filtered by passing the coating composition through one or more filters of the filtering assembly, having an absolute pore size rating in the range from approximately 0.05 to approximately 5 microns, at a temperature less than approximately 105° F. (40° C.), and at a pressure drop ?P across the filtering assembly of at most approximately 80 psig, wherein the ratio of pressure drop (mPa) to viscosity (mPa·s), which is dependent upon filtering temperature, minimizes the filtration factor to ?250,000 s?1.

Abstract: A livestock sorter includes a weighing scale within a confining cage for obtaining a weight of the animal to be sorted depending on its reaching a predetermined market weight. Front and rear gates are each formed by two gate panels which are pivotal about a vertical axis at an outer edge of the gate panel. The gate panels are opened and closed by symmetrical levers and links connected from the gate panel to an actuating member slidable in a slide track along the midline of the container in response to an actuating force from a drive member. The actuating member, the links and the levers are arranged overcenter against an end stop of the guide track such that, with the gate panels in the closed position, force from the animal on the gate panels tending to open the gate panels provides no force through the links and the actuating member to the drive member.

Abstract: A method is provided to manufacture a coated substrate, such as an optical fiber, without undesirable point lumps. The method filters a coating composition while controlling the filtering temperature, pressure drop across a filtering assembly, and filter pore size to achieve a resulting filtration factor not greater than 250,000 s−1. The filtration factor is a function of filtering temperature and pressure drop across the filtering assembly. Typically, the coating composition is filtered by passing the coating composition through one or more filters of the filtering assembly, having an absolute pore size rating in the range from approximately 0.05 to approximately 5 microns, at a temperature less than approximately 105° F. (40° C.