Abstract: A data processing system includes first, second, and third agents connected to a shared bus. The third agent is able to receive information via the shared bus from the first agent or from the second agent. The third agent includes a skew compensation circuit to determine signal skew in signal received via the shared bus and to compensate for the skew by adding delay into selected signals of the bus. The skew compensation circuit determines whether the first agent or the second agent is the sender of information received by the third agent via the shared bus. The skew compensation circuit alters the skew compensation based on the identity of the sender such that the delay into the bus signals is specific to the corresponding sender.

Abstract: A memory system for a data processor whereby a plurality of memory devices, or storage chips, are coupled to a memory controller. There may be one, two, or more such memory devices, wherein some of the memory devices may be coupled to the memory controller via a single data bus, with an alternative embodiment including a second plurality of such memory devices coupled to the memory controller via a second data bus. Two separate clock buses are used to transport data between the memory controller and the various memory devices. A first clock bus is used to synchronize the transfer of data from the memory controller to a memory device. This clock bus will have a clock signal generated at the memory controller through a clock generation circuitry as a function of a system clock received by the memory controller.

Abstract: A synchronizer for providing a source-synchronized clock bus reduces the effect of clock skew during the signal capturing process. The synchronizer includes at least one capture latch in the capture clock domain for capturing the signal, at least one storage latch for storing the signal coupled to the at least one capture latch, and a multiplexer coupled to the at least one storage latch. The multiplexer synchronizes data transfer of the at least one storage latch and the at least one capture latch, and an internal latch in the internal clock domain. The signal is controlled and processed by strobe signals and clock signals from the sending chip.

Abstract: A method for manufacturing package structure integrated circuit chips having a heat spreader is disclosed. A wiring substrate is first provided. An integrated circuit chip, having a first surface and a second surface, is then electrically and mechanically connected to the wiring substrate via a first set of solder joints. A heat spreader is subsequently connected to the second surface of the integrated circuit chip via a second set of solder joints. The heat spreader includes an adhesion-promotion layer on a silicon layer.

Abstract: In order to transmit several data words in succession over a bus between components in a data processing system, the skew between the various bus lines has to be compensated in order that each data word is accurately received. The skew compensation is implemented by setting predetermined delays on certain bus lines in response to the comparison of a test pattern with an ideal situation.

Abstract: A decoupling capacitor for an integrated circuit is operatively coupled to a supply and to control circuitry for isolating the capacitor. The control circuitry automatically isolates the capacitor in response to a current through the capacitor exceeding a certain threshold, but tends to restore the capacitor to operation if the current is merely caused by momentary conditions, rather than substantial failure of the capacitor. The control circuitry includes a first control device for automatically switching to an off state to isolate the capacitor in response to a voltage produced by the current exceeding a certain threshold. A discharging device tends to discharge the voltage and automatically turn on the first device when the current is caused by momentary conditions. The discharging device may include a control device responsive to an external control signal for switching the first control device on and off.

Abstract: An improved package structure for integrated-circuit chips is disclosed. In accordance with a preferred embodiment of the present invention, the integrated-circuit packaged structure comprises a wiring substrate, an integrated-circuit chip, and a heat spreader. The integrated-circuit chip has a first surface and a second surface, wherein the first surface is electrically and mechanically connected to the wiring substrate via a first set of solder joints. The heat spreader is connected to the second surface of the integrated-circuit chip via a second set of solder joints. The heat spreader includes an adhesion-promotion layer on top of a silicon layer, such that heat generated from the integrated-circuit chip can be efficiently transmitted to and subsequently dissipated by the heat spreader.

Abstract: Disclosed is a technique for testing functional circuit units of an integrated circuit. For each separate functional circuit unit desired to be tested, a capacitor is connected to each input while a diode is connected to each output. An electron beam then selectively renders first the selected capacitors conductive, permitting the application of a desired input pattern, and then the selected diode is rendered conductive in the reverse direction, permitting sensing.