Abstract: A frame buffer memory organization which is capable of accessing a pixel aligned M by N array of contiguous pixels on the screen from a frame buffer memory constructed of an M by N array of memory chips by driving a common address bus to all the memory chips, and by driving N RAS wires horizontally across the memory chip array and M CAS wires vertically down the memory chip array. The writing of individual pixels in this array is enabled by energizing the write enable pins to each memory chip directly.The data wires in the memory organization are tied together such that M horizontal pixels in a single row can be read or written simultaneously. Additionally, all M and N pixels may be written simultaneously if the data in all vertical columns is the same.The frame buffer includes a selectively energizable plane mask for disabling desired planes of accessed pixels.

Abstract: A display adapter for displaying graphics data in pixel form on a high resolution display monitor includes a digital signal processor for managing adapter resources and controlling coordinate transformations, a system storage which is divided into a first portion for storing instructions for the digital signal processor and the second portion for storing data representing information to be displayed, an input buffer for permitting asynchronous and overlapped communication between the graphics display adapter and a host computer to speed operation of the system, a pixel processor for drawing vectors and manipulating areas to be displayed on the monitor, a bit mapped frame buffer, a color palette connected to outputs of the frame buffer for providing appropriate color signals to the high resolution monitor and a cursor circuit for controlling display of a cursor on the screen on the monitor.

Abstract: A pixel processor includes a plurality of pixel slice processors and the architecture is arranged so that the pixel length is extendible by merely increasing the number of pixel slice processors. Each of the pixel slice processors is firstly interconected with other pixel slice processors, and includes a plurality of registers, gates and multiplexers for selectively presenting to a processing means data derived from a variety of sources, including a frame buffer. The output of the processing means can be stored back in the frame buffer or directed to one or more registers in the associated pixel slice processor or/and to registers in other pixel slice processors. SIMD operation is accomplished for pixel lengths which are equal to or larger than the bit capacity of the pixel slice processors. In a particular embodiment of the invention, SIMD operation is effected on pixel lengths larger than the bit capacity of the pixel slice processors.

Abstract: A color graphic processor includes one or more processing elements responsive to pixel data provided by a frame buffer. The processing element stores pixels from the frame buffer in source and destination registers. The arithmetic logic unit (ALU) portion of the processing element includes a random access memory (RAM) addressed by the registers to produce a result pixel value which can be written back to the frame buffer. The RAM can implement a wide variety of pixel operations by loading the RAM with operation specific data.

Abstract: A multichannel data path architecture which assists a host processor in communication with the frame buffer in order to increase the overall system performance. The architecture provides automatic frame buffer data path rearrangement depending on the pixel address and the host data interpretation. It utilizes a minimum of shift registers, accumulators and control circuitry to provide the requisite storage, reconfiguration and frame buffer access functions. The architecture extends bit-blt (bit block transfer) conventional operations in order to provide high quality "antialiased" text and graphics directly in the architecture without requiring the calculation of colors by the host processor. Finally, it assists the "burst" mode update of an arbitrary single plane of a frame buffer, which is especially important when high denisty chips are used for the frame buffer implemenation.

Abstract: A vector generator for us with an all-points-addressable frame buffer capable of the non-word aligned access, simultaneously, of a square M by N array of pixels providing fast vector drawing independently of vector slope and position in the whole screen area of an attached display monitor. The vector generator utilizes a triangular logic matrix together with a line drawing unit to generate M vector bits lying in an M by N square matrix of the screen of an attached monitor in one memory cycle of the frame buffer and uses the generated matrix to generate a direct mask for the frame buffer whereby the M bit vector may be stored in a single memory cycle.

Abstract: A display controller provides multiple different resolutions by selectively enabling different combinations of shift registers between the frame buffer and video look-up tables (VLTs). The VLTs are partitioned, with different partitions being programmed identically in accordance with the values of only the number of address bits which will be active from the shift registers at any one time.

Abstract: Radiographic imaging apparatus and methods for operating such apparatus, such apparatus being adapted to provide energy aberration correction, nonlinearity correction, and uniformity correction. The apparatus includes an energy filter which accepts or rejects a detected event for further processing and imaging. An accepted event has position data corrected for linearity by a linearity corrector. The linearity corrected position data is used if, and only if, certain uniformity criteria are complied with as determined by a uniformity correction process. The uniformity corrector operates concurrently with the linearity corrector by responding to nonlinearity corrected position data of events accepted by the energy filter.