Abstract: An apparatus and method for ring interconnect bandwidth scaling. In some embodiments, interfaces of first and second ring interconnects couple a plurality of cores and a plurality of cache slices. The ring interconnects provide packet-based communication in a first direction and a second direction and the interfaces include egress buffers to queue packets waiting to be transmitted over the first ring interconnect and the second ring interconnect. The plurality of interfaces are controlled to route packets between the cores and the cache slices in accordance with one of a plurality of modes, including a shortest path mode and a dynamic routing mode to be entered when the detected packet occupancy of at least one egress buffer reaches a first defined threshold.

Abstract: An apparatus and method for data sharing optimizations. One embodiment of a processor comprises: a plurality of cores; a plurality of caches to store cachelines read from memory by the plurality of cores; cache management circuitry to manage coherency of the cachelines by performing snoops including probes and confirms, the cache management circuitry to: determine a number of outstanding probes and a number of outstanding confirms within a snoop monitoring window; and prioritize confirms over probes or prioritize probes over confirms based, at least in part, on the number of outstanding confirms relative to the number of outstanding probes.

Abstract: Techniques and mechanisms for efficiently providing access to cached data. In an embodiment, a cache coherency engine comprises circuitry to provide a snoop filter which stores entries each corresponding to a respective line of one or more caches. The one or more caches comprise a first cache which includes a first set, and the snoop filter includes a first plurality of sets which are each configured to be available to represent a line of the first set. In another embodiment, the one or more caches comprise multiple caches which each comprise a respective first set, wherein, for each set of the first plurality of sets, any line in the multiple caches which is to be represented by that each set is to be a line in the respective first sets of the multiple caches.

Abstract: Apparatus and method for performance and energy efficient compute. One example processor package comprises: an efficient core cluster comprising first cores and one or more caches; a performance core cluster comprising second cores and a second one or more caches; a memory controller to couple the efficient core cluster and the performance core cluster of cores to a memory; wherein responsive to a request for a first cache line originating from the performance core cluster which hits the snoop filter, the home agent is to snoop at least one of the first one or more caches to ensure coherency of the first cache line; and wherein responsive to a request for a second cache line originating from the efficient core cluster which misses the snoop filter, the home agent is to snoop at least one of the second one or more caches to ensure coherency of the second cache line.

Abstract: Power may be reduced by dynamically controlling coherent cache fabric (CCF) utilization to efficiently support the number of active cores. In some embodiments, this may be achieved by dynamically reducing or even bypassing the CCF.

Abstract: Systems, methods, and apparatuses relating to circuitry to implement dynamic bypassing of last level cache are described. In one embodiment, a hardware processor includes a cache to store a plurality of cache lines of data, a processing element to generate a memory request and mark the memory request with a reuse hint value, and a cache controller circuit to mark a corresponding cache line in the cache as more recently used when the memory request is a read request that is a hit in the cache and the reuse hint value is a first value, and mark the corresponding cache line in the cache as less recently used when the memory request is the read request that is the hit in the cache and the reuse hint value is a second, different value.

Abstract: An embodiment of an integrated circuit may comprise a core, and a cache controller coupled to the core, the cache controller including circuitry to identify data from a working set for dynamic inclusion in a next level cache based on an amount of re-use of the next level cache, send a shared copy of the identified data to a requesting core of one or more processor cores, and maintain a copy of the identified data in the next level cache. Other embodiments are disclosed and claimed.

Abstract: Methods and apparatus relating to leveraging system cache for performance cores are described. In an embodiment, a system cache stores one or more cachelines that are to be evicted from a processor cache. Logic circuitry determines whether to store the one or more cachelines in the system cache based at least in part on comparison of a threshold value with a hit rate associated with the one or more cachelines. Other embodiments are also disclosed and claimed.

Abstract: Examples described herein relate to a cache fabric that includes a first layer of a group of routers and includes a second layer of a plurality of clusters of cache controllers. A router of the group of routers can be accessible via an interface that is to receive a memory access request from a processor and select from a group of cache controllers based on a cluster identifier and memory address and provide the memory access request to the selected group of cache controllers. The selected group of cache controllers can receive the memory access request and service a memory access request from a cache device or forward the memory access request to a second cache controller associated with the cache device or a second cache device.

Abstract: Techniques and mechanisms for efficiently providing access to cached data. In an embodiment, a cache coherency engine comprises circuitry to provide a snoop filter which stores entries each corresponding to a respective line of one or more caches. The one or more caches comprise a first cache which includes a first set, and the snoop filter includes a first plurality of sets which are each configured to be available to represent a line of the first set. In another embodiment, the one or more caches comprise multiple caches which each comprise a respective first set, wherein, for each set of the first plurality of sets, any line in the multiple caches which is to be represented by that each set is to be a line in the respective first sets of the multiple caches.

Abstract: An embodiment of an integrated circuit may comprise a core, and a cache controller coupled to the core, the cache controller including circuitry to identify data from a working set for dynamic inclusion in a next level cache based on an amount of re-use of the next level cache, send a shared copy of the identified data to a requesting core of one or more processor cores, and maintain a copy of the identified data in the next level cache. Other embodiments are disclosed and claimed.

Abstract: An embodiment of an integrated circuit may comprise a core, and a cache controller coupled to the core, the cache controller including circuitry to identify single re-use data evicted from a core cache, and retain the identified single re-use data in a next level cache based on an overall re-use of the next level cache. Other embodiments are disclosed and claimed.

Abstract: Systems, methods, and apparatuses relating to circuitry to implement dynamic bypassing of last level cache are described. In one embodiment, a hardware processor includes a cache to store a plurality of cache lines of data, a processing element to generate a memory request and mark the memory request with a reuse hint value, and a cache controller circuit to mark a corresponding cache line in the cache as more recently used when the memory request is a read request that is a hit in the cache and the reuse hint value is a first value, and mark the corresponding cache line in the cache as less recently used when the memory request is the read request that is the hit in the cache and the reuse hint value is a second, different value.

Abstract: Technologies are provided in embodiments to dynamically fill a shared cache. At least some embodiments include determining that data requested in a first request for the data by a first processing device is not stored in a cache shared by the first processing device and a second processing device, where a dynamic fill policy is applicable to the first request. Embodiments further include determining to deallocate, based at least in part on a threshold, an entry in a buffer, the entry containing information corresponding to the first request for the data. Embodiments also include sending a second request for the data to a system memory, and sending the data from the system memory to the first processing device. In more specific embodiments, the data from the system memory is not written to the cache based, at least in part, on the determination to deallocate the entry.

Abstract: Systems and methods are disclosed for initialization of a processor. Embodiments relate to alleviating any BIOS code size limitation. In one example, a system includes a memory having stored thereon a basic input/output system (BIOS) program comprising a readable code region and a readable and writeable data stack, a circuit coupled to the memory and to: read, during a boot mode and while using a cache as RAM (CAR), at least one datum from each cache line of the data stack, and write at least one byte of each cache line of the data stack to set a state of each cache line of the data stack to modified, enter a no-modified-data-eviction mode to protect modified data from eviction, and to allow eviction and replacement of readable data, and begin reading from the readable code region and executing the BIOS program after entering the no-modified-data-eviction mode.

Abstract: Technologies are provided in embodiments to dynamically fill a shared cache. At least some embodiments include determining that data requested in a first request for the data by a first processing device is not stored in a cache shared by the first processing device and a second processing device, where a dynamic fill policy is applicable to the first request. Embodiments further include determining to deallocate, based at least in part on a threshold, an entry in a buffer, the entry containing information corresponding to the first request for the data. Embodiments also include sending a second request for the data to a system memory, and sending the data from the system memory to the first processing device. In more specific embodiments, the data from the system memory is not written to the cache based, at least in part, on the determination to deallocate the entry.

Abstract: An indication of a first cache entry to be removed from a cache, the first cache entry corresponding to a first memory address in a memory may be received. A second memory address in the memory based at least in part on the first memory address may be identified. A request to identify a second cache entry in the cache corresponding to the second memory address and to determine whether a removal policy is satisfied may be sent. A response to the request, the response comprising an indication of the second cache entry to be removed from the cache based at least in part on the request may be sent. The first cache entry and the second cache entry from the cache may be removed. Data corresponding to the first and second cache entries to the memory with a single page file access may be written.

Abstract: Systems, methods, and processors to reduce redundant writes to memory. An embodiment of a system includes: a plurality of processors; a memory coupled to one of more of the plurality of processors; a cache coupled to the memory such that a dirty cache line evicted from the cache is written to the memory; and a redundant write detection circuitry coupled to the cache, wherein the redundant write detection circuitry to control write access to the cache based on a redundancy check of data to be written to the cache. The system may include a first predictor circuitry to deactivate the redundant write detection circuitry responsive to a determination that power consumed by the redundancy check is greater than the power it saves, or a second predictor circuitry to deactivate the redundant write detection circuitry when memory bandwidth saved from performing the redundancy check is not being utilized by memory reads.

Abstract: Systems and methods are disclosed for initialization of a processor. Embodiments relate to alleviating any BIOS code size limitation. In one example, a system includes a memory having stored thereon a basic input/output system (BIOS) program comprising a readable code region and a readable and writeable data stack, a circuit coupled to the memory and to: read, during a boot mode and while using a cache as RAM (CAR), at least one datum from each cache line of the data stack, and write at least one byte of each cache line of the data stack to set a state of each cache line of the data stack to modified, enter a no-modified-data-eviction mode to protect modified data from eviction, and to allow eviction and replacement of readable data, and begin reading from the readable code region and executing the BIOS program after entering the no-modified-data-eviction mode.