Abstract: A semiconductor device including a stacked structure including first vertically stacked channel regions positioned over second vertically stacked channel regions. The first and second vertically stacked channel regions have a mid dielectric layer positioned therebetween. A structure is present having a first portion in electrical communication with the first vertically stacked channel regions and a second portion in electrical communication with the second vertically stacked channel regions. The semiconductor device also includes at least one two-component gate cut structure present adjacent to the gate all around structure. A first component of the two-component gate cut structure in positioned on one side of the mid dielectric layer adjacent to the first portion of the gate structure, and a second component of the two-component gate cut structure is positioned on a second side of the mid dielectric layer adjacent to the second portion of the gate structure.

Abstract: Yielding and routable circuit co-design using viabars, including: creating, in a first metal layer of an integrated circuit design, a first interconnect having a slack portion vertically coinciding with a second interconnect of a second metal layer of the integrated circuit design; creating, in the integrated circuit design, a first via interconnecting the first interconnect and the second interconnect; determining, after block-level signal routing of the integrated circuit design and based on one or more design rules, that the first via can be extended into the slack portion; and extending, based on the determination that the first via can be extended, the first via into a viabar interconnecting the first metal layer and the second metal layer.

Abstract: A semiconductor structure with two adjacent semiconductor devices of a plurality of semiconductor devices that have a backside contact that connects two adjacent source/drains of the two adjacent semiconductor devices to a backside power rail. The semiconductor provides the backside contact with a larger bottom contact area with the backside power rail than a combined contact area of the two top surfaces of the backside contact with the two adjacent source/drains.

Abstract: Apparatus for mitigating latch-up within semiconductor devices. A semiconductor device includes a first conductor, a second conductor, and a first gate conductor. The first conductor extends in a first direction, receives a first power supply signal, and is connected to a first electrode. The second conductor extends in the first direction, receives a second power supply signal different from the first power supply signal, and is connected to a second electrode. The first conductor is offset from the second conductor in a second direction perpendicular to the first direction in a top-down view to mitigate formation of parasitic devices within the semiconductor device electrically connecting the first conductor with the second conductor. The first gate conductor is disposed adjacent to the first conductor and the second conductor, is disposed on the first electrode and the second electrode, and receives an input signal.

Abstract: A semiconductor structure including a gate contact above and in direct contact with a top surface of a gate. a backside wiring layer below a backside power delivery network. and a contact via extending between the gate contact and the backside wiring layer.

Abstract: A semiconductor structure comprises a first transistor and a second transistor. The first transistor comprises a first input source/drain region and a first output source/drain region, and the second transistor comprises a second input source/drain region and a second output source/drain region. The first input source/drain region and the second input source/drain region are connected to a first source/drain contact, and the first output source/drain region and the second output source/drain region are connected to a second source/drain contact. The first source/drain contact and the second source/drain contact on a same side of the semiconductor structure.

Abstract: Aspects of the invention include systems and methods configured to provide hierarchical circuit designs that makes use of a color decomposition of library cells having boundary-aware color selection. A non-limiting example computer-implemented method includes placing a plurality of shapes within a hierarchical level of a chip design. The plurality of shapes can include a top boundary shape, a bottom boundary shape, one or more center boundary shapes, and one or more internal shapes. A hierarchical hand-off region is constructed by pinning the top boundary shape to a first mask, pinning the bottom boundary shape to a second mask, and pinning the one or more center boundary shapes to a same mask. The same mask is selected from one of the first mask and the second mask.

Abstract: A structure including a plurality of nanosheet transistors each comprising a gate. A gate protrusion extends from the gate towards the backside of one of the plurality of electronic devices. A first dielectric liner is located flush against the sidewalls of the gate protrusion. A contact via connected to a backside surface of the gate protrusion. A second dielectric liner located flush again the sidewalls of the contact via.

Abstract: A semiconductor structure includes a first backside metal rail that extends across the structure and a second backside metal rail parallel and adjacent to the first backside metal rail. The first and second backside metal rails bound a first circuit row. The structure also includes a backside signal wire that interrupts the second backside metal rail; and a third backside metal rail that extends across the structure parallel and adjacent to the second backside metal rail. The second and third backside metal rails bound a second circuit row. The structure also includes gate metal pitches, which extend across the structure perpendicular to the backside metal rails. The structure also includes a frontside signal wire above the gate metal pitches; and a signal via that penetrates the structure and connects the backside signal wire to the frontside signal wire.

Abstract: Semiconductor devices and methods of forming the same include a channel over a backside layer. A dielectric fill is on the backside layer, including a first dielectric material. A gate conductor is on the channel and makes electrical contact with the backside layer through the dielectric fill. A dielectric liner is on sidewalls of the dielectric fill, including a second dielectric material, in contact with the gate conductor at the dielectric fill.

Abstract: Embodiments herein include semiconductor structures that may include a first field-effect transistor (FET) comprising a first source/drain (S/D), a second FET comprising a second S/D squarely above the first S/D, and a shared S/D contact. The shared S/D may include a recessed portion between the first S/D and the second S/D, a side portion above the recessed portion, and a top portion above the second S/D. The side portion may contact a lateral side of the second S/D.

Abstract: A semiconductor structure is provided that includes a gate structure that is wired to a backside signal line through a backside gate contact extension and a backside skip-level through via. The backside skip-level through via has a dielectric spacer located on a sidewall thereof and a portion of the backside skip-level through via is positioned between a pair of backside power rails that are located in a first backside metal level that is located beneath a second backside metal level that includes the backside signal line.

Abstract: Direct measurement of a latch timing window includes, for each of a plurality of predetermined delay times: providing a first signal to a data input of a first latch of a ring oscillator circuit via a delay block configured to delay the first signal by the predetermined delay time; providing the first signal to a first logic clock buffer (LCB); generating a clock signal by the first LCB responsive to receiving the first signal; providing the clock signal to a clock input of the first latch; and determining from an output of the ring oscillator circuit that the ring oscillator circuit is in either an oscillating state or a non-oscillating state. At least one timing window parameter for the first latch is determined based on one or more of the plurality of delay times that are associated with an oscillating state of the ring oscillator circuit.

Abstract: Embodiments for power generation include defining a power tile within a power distribution network having a grid of power rails, the power tile having logic gates, and applying an initial power grid pattern from a plurality of power grid patterns for the power tile such that initial power grid pattern relates to timing characteristics of the logic gates of the power tile. The power grid patterns each have a different number of connectors connecting one power rail to another power rail in the grid of power rails. A subsequent power grid pattern is selected from the power grid patterns for the power tile such that the subsequent power grid pattern meets a threshold condition for the timing characteristics of the logic gates of the power tile. The timing characteristics for the logic gates are determined based on a voltage drop associated with the subsequent power grid pattern.

Abstract: Aspects of the invention include a computer-implemented method of chip design. The computer-implemented method of chip design include establishing an architecture with alternating rows of differently colored chip-level shapes. Cells are constrained to be rectangular with restricted widths. Constraint-observing parent and child cells are generated and respectively include boundaries with alternating rows of differently colored cell-level shapes for disposition in the architecture. The parent cell is positioned in the architecture such that the cell-level shapes thereof exhibit row and color alignment with the chip-level shapes. Child cells exhibiting uni-axial or multi-axial reflectivity are instantiated in the parent cell. A color solution is instantiated for each child cell in the parent cell such that cell-level shapes of the child cells exhibit row and color alignment with the cell-level shapes of the parent cell.

Abstract: Method and structures for shared (dual) sources for a single device in semiconductor devices such as very-large-scale integration (VLSI) devices. The shared-source improves or increases a current that passes through the device (e.g., to a drain region associated with the shared-source), which in turn increases a performance of the device. Example improvements may include a delay improvement of the device and associated logic paths and/or a power improvement for the device. The method includes operations for design improvements during a design process by implementing shared-sources in a semiconductor device design.

Abstract: Method and apparatus for generating an updated power delivery network. Generating the power delivery network includes determining power characteristics for a power delivery network of a circuit design based on logic cells of the circuit design. The power delivery network includes power wires and power staples connecting pairs of the power wires to each other. Further a first one or more of the power staples is remove from the power delivery network based on the power characteristics. Signal wires for the logic cells are routed after removing the first one or more of the power staples. Routing the signal wires includes routing a first signal wire of the signal wires in a routing track corresponding to the first one or more of the power staples.

Abstract: Apparatus for mitigating latch-up within semiconductor devices. A semiconductor device includes a first conductor, a second conductor, and a first gate conductor. The first conductor extends in a first direction, receives a first power supply signal, and is connected to a first electrode. The second conductor extends in the first direction, receives a second power supply signal different from the first power supply signal, and is connected to a second electrode. The first conductor is offset from the second conductor in a second direction perpendicular to the first direction in a top-down view to mitigate formation of parasitic devices within the semiconductor device electrically connecting the first conductor with the second conductor. The first gate conductor is disposed adjacent to the first conductor and the second conductor, is disposed on the first electrode and the second electrode, and receives an input signal.

Abstract: Aspects of the invention include systems and methods for implementing a CMOS circuit design that uses a sea-of-gates fill methodology to provide latch-up avoidance. A non-limiting example computer-implemented method includes identifying a fill cell in the circuit design. The fill cell can include a power rail, a ground rail, and a field-effect transistor (FET) electrically coupled to the power rail through a via. The method can include disconnecting the via from the power rail and moving the via to a disconnected node in the fill cell. Moving the via decouples a source or drain of the fill cell from a well of the fill cell, preventing latch-up while maintaining via and metal shape density.

Abstract: Embodiments for power generation include defining a power tile within a power distribution network having a grid of power rails, the power tile having logic gates, and applying an initial power grid pattern from a plurality of power grid patterns for the power tile such that initial power grid pattern relates to timing characteristics of the logic gates of the power tile. The power grid patterns each have a different number of connectors connecting one power rail to another power rail in the grid of power rails. A subsequent power grid pattern is selected from the power grid patterns for the power tile such that the subsequent power grid pattern meets a threshold condition for the timing characteristics of the logic gates of the power tile. The timing characteristics for the logic gates are determined based on a voltage drop associated with the subsequent power grid pattern.