Abstract: Methods and systems for a circuit similarity metric for semiconductor testsite coverage. One or more unique values for each of a set of measures for each circuit layout of a plurality of circuit layouts are identified and a pairwise comparison across the set of measures is conducted for a selected pair of the plurality of circuit layouts to derive a similarity score for the selected pair of circuit layouts. The similarity score is incremented for the selected pair in response to the selected pair of circuit layouts sharing a same unique value and the similarity score is decremented for the selected pair in response to one circuit layout of the selected pair of circuit layouts having a unique value that the other circuit layout of the selected pair does not contain.

Abstract: Methods and systems for a circuit similarity metric for semiconductor testsite coverage. One or more unique values for each of a set of measures for each circuit layout of a plurality of circuit layouts are identified and a pairwise comparison across the set of measures is conducted for a selected pair of the plurality of circuit layouts to derive a similarity score for the selected pair of circuit layouts. The similarity score is incremented for the selected pair in response to the selected pair of circuit layouts sharing a same unique value and the similarity score is decremented for the selected pair in response to one circuit layout of the selected pair of circuit layouts having a unique value that the other circuit layout of the selected pair does not contain.

Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Abstract: A method for performing timing closure on VLSI chips in a distributed environment is described. Abstracting the physical and timing resources of a chip and providing an asynchronous method of updating that abstraction allows multiple partitions of a chip to be optimized concurrently. A global view of physical and timing resources is supplied to local optimizations which are applied concurrently to achieve timing closure. Portions of the hierarchy are optimized in separate processes. Partitioning of the chip is performed along hierarchical lines, with each process owning a single partition in the hierarchy. The processes may be executed by a single computer, or spread across multiple computers in a local network. While optimizations performed by a single process are only applied to its given portion of the hierarchy, decisions are made in the context of the entire hierarchy. These optimizations include placement, synthesis, and routing.

Abstract: A method (and system) of applying transforms for modifying a plurality of domains concurrently in a design space, includes creating a sequence of more and less granular placement and netlist modification transforms. A converging design process flow is created by a flexible mechanism in which a select combination of fine-grained transforms are applied to optimize the netlist and placement of a design.

Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Abstract: A high-performance gate library is augmented with tapered gates. The widths of the stacked devices are varied to reduce the delay through some of the input pins. For example in a tapered NAND gate the bottom devices in the NFET stack are have longer widths than the top device to achieve smaller top input to output pin delay at the expense of larger bottom input to output pin delay. The method of using synthesis algorithms modifies the input net to gate pin connections and swaps traditional non-tapered gates with tapered gates to improve the delay of the timing critical paths. The latest arriving gate input net is swapped with the net connected to the top pin. The gate is then converted to a tapered gate provided the paths through the bottom gate input(s) that are not timing critical.

Abstract: A method for performing timing closure on VLSI chips in a distributed environment is described. Abstracting the physical and timing resources of a chip and providing an asynchronous method of updating that abstraction allows multiple partitions of a chip to be optimized concurrently. A global view of physical and timing resources is supplied to local optimizations which are applied concurrently to achieve timing closure. Portions of the hierarchy are optimized in separate processes. Partitioning of the chip is performed along hierarchical lines, with each process owning a single partition in the hierarchy. The processes may be executed by a single computer, or spread across multiple computers in a local network. While the optimizations performed by a single process are only applied to its given portion of the hierarchy, decisions are made in the context of the entire hierarchy. These optimizations include placement, synthesis, and routing.

Abstract: The present invention concerns a method for maintaining regularity in a netlist during logic synthesis. The method determines a global regularity for the netlist. The method determines a group of elements in the netlist having similar regularity signatures. Further, the method applies a transform to the group of elements.

Abstract: A high-performance gate library is augmented with tapered gates. The widths of the stacked devices are varied to reduce the delay through some of the input pins. For example in a tapered NAND gate the bottom devices in the NFET stack are have longer widths than the top device to achieve smaller top input to output pin delay at the expense of larger bottom input to output pin delay. The method of using synthesis algorithms modifies the input net to gate pin connections and swaps traditional non-tapered gates with tapered gates to improve the delay of the timing critical paths. The latest arriving gate input net is swapped with the net connected to the top pin.

Abstract: A technology mapping method and device for mapping cost functions on directed acyclic graphs, using decoupled matching and covering and circumventing the memory explosion usually caused by this decoupling. Multiple matches are generated at the head of a wavefront process and embedded within the network. Covering is done at the tail of the wavefront to optimize one or more cost functions.

Abstract: Size independent timing optimization is performed on an initial circuit design using gain based models for logic cell types. A component library containing various logic elements in a plurality of sizes is provided and a single gain based model for each logic element (cell type) is created therefrom. Initial conditions for gain and delay are then established for each cell type. Gain based optimization, which is size independent, is then performed on the initial circuit design. The optimized size independent solution is then transformed into a realizable discrete circuit solution.