Abstract: An intermediate component can be provided between initiator components (from which access requests are originated) and target components (that are to be accessed via the access requests). The intermediate component can encode, decode, and/or bypass the encoding process of address bits to ensure that address bits of the access requests are in a format that is compatible with access of the respective target component.

Abstract: An example method can include performing a first sensing operation associated with circuitry on a system on chip (SoC) to determine a first data value, performing a second sensing operation associated with circuitry of a sensor the SoC to determine a second data value, responsive to the first data value and the second data value being the same data value, determining that a clock margin is sufficient, and responsive to the first data value and the second data value being different data values, determining that a clock margin is insufficient. In some examples, a voltage-frequency operating combination associated with at least one operation of the SoC can be adjusted to a particular stored voltage-frequency operating combination that provides a sufficient clocking margin.

Abstract: An example method for scan-based voltage frequency scaling can include performing a plurality of at-speed scan operation on a system on chip (SoC) at a plurality of respective voltage values. The example method can include entering data gathered from at least one of the plurality of at-speed scan operations into a database. The entered data is associated with the respective plurality of voltage value. The example method can include determining a particular voltage value of the respective plurality of voltage values at which a parameter of the SoC reaches a threshold. The example method can include indicating the determined particular voltage in the database. The indicated determined particular voltage in the database can be used for performing one or more operations using the SoC.

Abstract: Current sensing circuitry and clock management circuitry provide current and clock frequency management. In one example, an apparatus can include a voltage regulator, current sensing circuitry configured to: detect a current associated with the voltage regulator of a system-on-chip (SoC), and determine when the current transitions from a first current to a second current; and clock management circuitry configured to: generate clocking signals for the SoC, select a gradient frequency alteration based on the detected current, and alter a frequency of the generated clocking signals to the gradient frequency alteration in response to the detected current transition.

Abstract: Voltage sensing circuitry and management circuitry provide voltage and clock frequency management. The voltage sensing circuitry may be configured to detect a voltage associated with a system-on-chip (SoC) and determine when the voltage transitions from a first voltage to a second voltage. The management circuitry may be configured to generate clocking signals for the SoC and alter a frequency of the generated clocking signals in response to the detected voltage transition.

Abstract: A first data entry is written to an address location of a memory resource that is neither a first physical address nor a last physical address. In response to a determination that a second data entry has a value that is greater than a value associated with the first data entry, the second data entry is written to an address location that is physically located between the address location of the memory resource to which the first data entry is written and the last physical address. In response to a determination that the second data entry has the value that is less than the value associated with the first data entry, the second data entry is written to an address location that is physically located between the address location of the memory resource to which the first data entry is written and the first physical address.

Abstract: A method includes determining a quantity of errors for a bit string based on a quantity of bits having a logical value of one within the bit string and writing an indication corresponding to the quantity of errors for the bit string to an array of memory cells. The method can further include determining that the quantity of errors for the bit string has reached a threshold quantity of errors and refraining from performing a subsequent operation to determine the quantity of errors for the bit string in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.

Abstract: An example method for voltage frequency scaling based on error rate can include performing a plurality of monitoring operations on a system on chip (SoC) at a respective plurality of voltage values (and/or plurality of frequency values and/or temperature values). The example method can include causing error rate data gathered from each of the plurality of monitoring operations to be entered into a database, wherein the entered error rate data is associated with the plurality of voltage values. The entered data is associated with the respective plurality of voltage value. The example method can include generating a plot using the error rate date in the database. The example method can include determining a particular voltage value greater than each of the plurality of voltage values based on the plot and a particular error rate associated with the particular voltage value.

Abstract: An example method for critical timing driven adjustable voltage frequency scaling can include performing sensing operations on a system on chip (SoC) at a respective plurality of time windows each associated with a particular data value, comparing at least two of the particular data values associated with at least two respective time windows of the plurality of time windows, in response to the at least two of the particular data values being a same data value, determining that a clock margin is above a threshold clock margin, and determining that a clock margin is below a threshold clock margin. In some instance, in response to determining that the clock margin is above the threshold clock margin, a clocking of the SoC can be adjusted, a voltage of at least one operation of the SoC can be adjusted, and/or a clocking frequency of at least one operation of the SoC, among other possibilities.

Abstract: A method includes determining a target total bit-error-rate (BER), calculating a target channel BER based on the target total BER, and training a channel to the calculated target channel BER by transmitting data over the channel in a loop from a physical input/output (PHY I/O) to a memory device, transmitting the test data over the channel in the loop from the memory device to the PHY I/O, wherein the data is looped from the memory device and back to the PHY I/O without being written to or road from the memory device, determining an actual channel BER based on the data transmitted to and received from the memory device, comparing the actual channel BER to the calculated target channel BER, and regulating a voltage value based on the comparison.

Abstract: A decoding operation is performed by receiving a command to read a correction matrix comprising multiple bit-values from memory of a decoder. The decoding operation also includes, responsive to receipt of the command, generating, using circuitry of a decoder, a predetermined correction matrix comprising a same bit-value. The decoding operation further includes providing the predetermined correction matrix to a decision engine to perform the decoding operation.

Abstract: A decoding operation is performed by altering at least one bit of the bit string from a first value to a second value and applying a bit mask to each bit of the bit string that is not altered from the first value to the second value. The decoding operation further includes writing an indication corresponding to a quantity of bits that have been altered from the first value to the second value to an array of memory cells, wherein the indication corresponds to a quantity of errors contained in the bit string, determining that the quantity of errors for the bit string has reached a threshold quantity of errors, and refraining from performing a subsequent operation to alter at least the one bit of the bit string, or a different bit of the bit string, or both, from the first value to the second value in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.

Abstract: A method includes generating, by circuitry resident on a memory device, parity information, appending parity information to data read from the memory device to generate a bit string comprising the data read from the memory device and parity information, transmitting the bit string from the memory device to a physical input/output (PHY I/O) device couplable to the memory device via a channel, calculating a parity mismatch value based on a comparison between received memory parity information and a calculated PHY I/O parity information, determining a target parity mismatch value, comparing the calculated parity mismatch value and the determined target parity mismatch value, and regulating a voltage in response to the comparison between the calculated parity mismatch value and the target parity mismatch value to maintain an actual channel error rate within an optimal range.

Abstract: A method includes generating, by circuitry resident on a memory device, parity information, appending parity information to data read from the memory device to generate a bit string comprising the data read from the memory device and parity information, transmitting the bit string from the memory device to a physical input/output (PHY I/O) device couplable to the memory device via a channel, calculating a parity mismatch value based on a comparison between received memory parity information and a calculated PHY I/O parity information, determining a target parity mismatch value, comparing the calculated parity mismatch value and the determined target parity mismatch value, and regulating a voltage in response to the comparison between the calculated parity mismatch value and the target parity mismatch value to maintain an actual channel error rate within an optimal range.

Abstract: A method includes determining that a power event involving a memory sub-system has occurred. The method further including in response to the determination that the power event has occurred, generating signaling indicative of performance of an operation to provide power to a plurality of memory components of the memory sub-system, where the signaling indicative of performance includes a power control signal is applied to a first memory component at a first time, and is applied to a second memory component at a second time that is subsequent to the first memory component entering a steady state.

Abstract: A hash corresponding to a bit string is generated. The hash corresponds to an address location in a data structure associated with the bit string. An index and a modifier correspond to the address location in the data structure corresponding to the hash associated with a first address location in the data structure are determined. In response to determining that the modifier has a first value associated therewith, index information corresponding to the bit string is written to the first address location in the data structure. In response to determining that the modifier has a second value other than the first value associated therewith, the index information corresponding to the bit string is written to a second address location in the data structure.

Abstract: A first memory resource is configured to store a data structure. The first memory resource is coupled to a second memory resource that is configured to store a plurality of data structures. A processing device is coupled to the first memory resource, the second memory resource, and a third memory resource. The processing device writes data entries to the data structure within the first memory resource, determine that the data structure within the first memory resource includes a threshold quantity of data entries, and write the contents of the data structure within the first memory resource to a data structure within the second memory resource. The processing resource is further configured to move the contents of the contents of the data structure in the second memory resource to the third memory resource by readdressing the entries written within the second memory resource to virtual addresses associated with the third memory resource.

Abstract: An example method for power emulation and estimation includes estimating a functional power consumption value associated with a memory system by determining: a scan-based power estimation, scan-based power measurement, a calibration factor from correlating the scan-based power estimation to the scan-based power measurement and a correlated functional power using the calibration factor. The calibration factor can be applied to a functional power estimation in order to achieve better accuracy.

Abstract: A plurality of flip-flops of an integrated circuit (IC) (e.g., an ASIC) are electrically connected in a predefined series. The scan input gate of any give flip-flop in the predefined series is electrically connected to one of a Q output gate or a Q-bar output gate of an adjacent flip-flop in the predefined series. A reset operation for the IC occurs by feeding a bit string of identical bits (e.g., all zeros) through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops without the need for resetting circuitry and accompanying power savings for the IC.

Abstract: An example method for voltage frequency scaling based on error rate can include performing a plurality of monitoring operations on a system on chip (SoC) at a respective plurality of voltage values (and/or plurality of frequency values and/or temperature values). The example method can include causing error rate data gathered from each of the plurality of monitoring operations to be entered into a database, wherein the entered error rate data is associated with the plurality of voltage values. The entered data is associated with the respective plurality of voltage value. The example method can include generating a plot using the error rate date in the database. The example method can include determining a particular voltage value greater than each of the plurality of voltage values based on the plot and a particular error rate associated with the particular voltage value.