Patents by Inventor Leon Zlotnik

Leon Zlotnik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12164375
    Abstract: A method includes determining a quantity of errors for a bit string based on a quantity of bits having a logical value of one within the bit string and writing an indication corresponding to the quantity of errors for the bit string to an array of memory cells. The method can further include determining that the quantity of errors for the bit string has reached a threshold quantity of errors and refraining from performing a subsequent operation to determine the quantity of errors for the bit string in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: December 10, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Leon Zlotnik, Eyal En Gad, Fan Zhou
  • Publication number: 20240354031
    Abstract: A method includes reading, from a memory array, a first counter identifier (ID) based on a pointer corresponding to an address location in the memory array in which the first counter ID is stored. The method includes incrementing the pointer to correspond to an address location in the memory array in which a second counter ID is stored and reading, from the memory array the second counter ID based on the pointer corresponding to the address location in the memory array in which the second counter ID is stored.
    Type: Application
    Filed: April 9, 2024
    Publication date: October 24, 2024
    Inventors: Leon Zlotnik, Leonid Minz
  • Publication number: 20240333305
    Abstract: A method for initiator identifier compression includes associating respective initiator identifiers (IID) of a sub-set of initiators coupled via an interconnection structure to a target with respective parallel target data streams and performing, via an individual target data stream of the target data streams, an operation associated with the target and an individual initiator included in the sub-set of initiators.
    Type: Application
    Filed: March 27, 2024
    Publication date: October 3, 2024
    Inventor: Leon Zlotnik
  • Publication number: 20240322675
    Abstract: A method includes supplying, via a first voltage regulator, a first supply voltage to a first voltage domain including circuitry configured to operate at the first supply voltage, supplying, via a second voltage regulator, a second supply voltage to a second voltage domain including circuitry configured to operate in a voltage zone, detecting a change in an error characteristic of data associated with the second voltage domain, and altering the second supply voltage to an altered supply voltage based on the change in the error characteristic.
    Type: Application
    Filed: March 12, 2024
    Publication date: September 26, 2024
    Inventors: Leon Zlotnik, Leonid Minz
  • Publication number: 20240321380
    Abstract: A method includes supplying, via a voltage regulator, a supply voltage to a first voltage domain and a second voltage domain, detecting a change in an error characteristic of data associated with the second voltage domain, and altering the supply voltage to an altered supply voltage based on the change in the error characteristic.
    Type: Application
    Filed: March 12, 2024
    Publication date: September 26, 2024
    Inventors: Leon Zlotnik, Leonid Minz
  • Patent number: 12088301
    Abstract: A plurality of flip-flops of an integrated circuit (IC) (e.g., an ASIC) are electrically connected in a predefined series. The scan input gate of any give flip-flop in the predefined series is electrically connected to one of a Q output gate or a Q-bar output gate of an adjacent flip-flop in the predefined series. A reset operation for the IC occurs by feeding a bit string of identical bits (e.g., all zeros) through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops without the need for resetting circuitry and accompanying power savings for the IC.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: September 10, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Leon Zlotnik, Leonid Minz, Yoav Weinberg
  • Patent number: 12086440
    Abstract: A first memory resource is configured to store a data structure. The first memory resource is coupled to a second memory resource that is configured to store a plurality of data structures. A processing device is coupled to the first memory resource, the second memory resource, and a third memory resource. The processing device writes data entries to the data structure within the first memory resource, determine that the data structure within the first memory resource includes a threshold quantity of data entries, and write the contents of the data structure within the first memory resource to a data structure within the second memory resource. The processing resource is further configured to move the contents of the contents of the data structure in the second memory resource to the third memory resource by readdressing the entries written within the second memory resource to virtual addresses associated with the third memory resource.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: September 10, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Leon Zlotnik, Brian Toronyi
  • Publication number: 20240296152
    Abstract: An apparatus includes a memory resource configured to store data entries in a data memory resource including a first data structure and a second data structure and a processing device coupled to the memory resource. The processing device is configured to determine a predicted address location in the first data structure, compare the predicted address location to at least one address threshold, alter the predicted address location to an altered predicted address location, determine an equivalent address location in a second data structure that is equivalent to the altered predicted address location, and write the data entry to the equivalent address location in the second data structure.
    Type: Application
    Filed: February 29, 2024
    Publication date: September 5, 2024
    Inventors: Leon Zlotnik, Sureshkumar Shastry Vemuri
  • Publication number: 20240296118
    Abstract: An apparatus includes a memory resource configured to store data entries in data structures including a first data structure and a second data structure and a processing device coupled to the memory resources. The processing device is configured to determine a predicted address location in the first data structure for a data entry, determine an equivalent address location in the second data structure, and write the data entry to the equivalent address location in the second data structure.
    Type: Application
    Filed: February 29, 2024
    Publication date: September 5, 2024
    Inventor: Leon Zlotnik
  • Publication number: 20240281042
    Abstract: A method includes measuring, by a plurality of thermal sensors coupled to a plurality of circuit portion areas of a memory sub-system, temperature information associated with the plurality of circuit portion areas. The method further includes generating a thermal map based on the measured temperature information associated with the plurality of circuit portion areas and determining, based on the thermal map, that at least one of the circuit portion areas has greater than a threshold probability of experiencing a thermal event. The method further includes operating processing circuitry coupled to the plurality of circuit portion areas to mitigate a thermal load associated with the at least one of the circuit portion areas that has greater than the threshold probability of experiencing the thermal event.
    Type: Application
    Filed: February 12, 2024
    Publication date: August 22, 2024
    Inventor: Leon Zlotnik
  • Publication number: 20240272811
    Abstract: A plurality of data entries are written in a first memory bank that comprises a portion of a data structure that is stored across a plurality of memory banks. For a subsequent data entry, a determination is made that the subsequent data entry has a value that is greater than a first data entry among the plurality of data entries in the first memory bank and less than a second data entry among the plurality of data entries in the first memory bank. The subsequent data entry is written to an address location in a second memory bank of the plurality of memory banks that is between a lowermost address location and an uppermost address location of the second memory bank and a first bit corresponding to the address location in the second memory bank to which the subsequent data entry was written is stored in the data structure.
    Type: Application
    Filed: February 2, 2024
    Publication date: August 15, 2024
    Inventors: Leon Zlotnik, Brian Toronyi
  • Patent number: 12044711
    Abstract: A voltage tracking circuit includes delay line blocks, a phase detector delay line block, phase detection circuitry, and a controller. The controller determines a first voltage based on a quantity of active delay line blocks among the plurality of delay line blocks and determines a second voltage based on information received from the phase detection circuitry. The controller determines a measured value of a voltage provided by the voltage regulator voltage based on the first voltage and the second voltage.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: July 23, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Leon Zlotnik, Leonid Minz
  • Publication number: 20240193144
    Abstract: A hash corresponding to a bit string is generated. The hash corresponds to an address location in a data structure associated with the bit string. An index and a modifier correspond to the address location in the data structure corresponding to the hash associated with a first address location in the data structure are determined. In response to determining that the modifier has a first value associated therewith, index information corresponding to the bit string is written to the first address location in the data structure. In response to determining that the modifier has a second value other than the first value associated therewith, the index information corresponding to the bit string is written to a second address location in the data structure.
    Type: Application
    Filed: December 7, 2023
    Publication date: June 13, 2024
    Inventors: Leon Zlotnik, Brian Toronyi
  • Publication number: 20240185898
    Abstract: A method includes receiving, by shift circuitry, a bit string comprising a plurality of bits and determining, based on a shifting indicator, a quantity of bits by which the bit string is to be shifted within the shift circuitry. The method further includes generating a shifted bit string by performing, by the shift circuitry, an operation to shift the bit string by the quantity of bits indicated by the shifting indicator and performing, by decision circuitry coupled to the shift circuitry, an operation to alter one or more of the plurality of bits of the shifted bit string from a logical value of one to a logical value of zero or from a logical value of zero to a logical value of one.
    Type: Application
    Filed: November 29, 2023
    Publication date: June 6, 2024
    Inventors: Eyal En Gad, Leon Zlotnik, Yoav Weinberg
  • Patent number: 11973504
    Abstract: An asynchronous multi-cycle reset synchronization circuit that can correlate any number of resets and synchronous clocks with simultaneous reset de-assertion and removal of reset assertion crossing hazards. The asynchronous multi-cycle reset synchronization circuit can also be paired with a synchronous multi-cycle reset synchronization circuit to correlate same domain asynchronous and synchronous resets. Also described is a synchronous reset multi-cycle synchronization circuit that correlates with any number of asynchronous resets and guarantees simultaneous reset de-assertion.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: April 30, 2024
    Assignee: INTEL CORPORATION
    Inventors: Leon Zlotnik, Lev Zlotnik, Jeremy Anderson
  • Publication number: 20240095123
    Abstract: A method includes determining a quantity of errors for a bit string based on a quantity of bits having a logical value of one within the bit string and writing an indication corresponding to the quantity of errors for the bit string to an array of memory cells. The method can further include determining that the quantity of errors for the bit string has reached a threshold quantity of errors and refraining from performing a subsequent operation to determine the quantity of errors for the bit string in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.
    Type: Application
    Filed: September 21, 2022
    Publication date: March 21, 2024
    Inventors: Leon Zlotnik, Eyal En Gad, Fan Zhou
  • Publication number: 20240097707
    Abstract: A decoding operation is performed by altering at least one bit of the bit string from a first value to a second value and applying a bit mask to each bit of the bit string that is not altered from the first value to the second value. The decoding operation further includes writing an indication corresponding to a quantity of bits that have been altered from the first value to the second value to an array of memory cells, wherein the indication corresponds to a quantity of errors contained in the bit string, determining that the quantity of errors for the bit string has reached a threshold quantity of errors, and refraining from performing a subsequent operation to alter at least the one bit of the bit string, or a different bit of the bit string, or both, from the first value to the second value in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.
    Type: Application
    Filed: September 21, 2022
    Publication date: March 21, 2024
    Inventors: Leon Zlotnik, Eyal En Gad
  • Publication number: 20240061485
    Abstract: A method includes receiving signaling indicative of a temperature of a circuit portion area of a memory sub-system and receiving signaling indicative of a voltage or a current of the circuit portion area of the memory sub-system. The method further includes generating, based on the signaling indicative of temperature of the circuit portion area and the signaling indicative of the voltage or the current of the circuit portion area, a voltage management control signal and transferring the voltage management control signal to a voltage regulator of the memory sub-system. The method further includes operating the voltage regulator in response to receipt of the voltage management control signal to generate a voltage signal.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Inventor: Leon Zlotnik
  • Publication number: 20240036596
    Abstract: A first voltage regulation circuit is coupled to a second voltage regulation circuit. Control circuitry is coupled to the first voltage regulation circuit and the second voltage regulation circuit. The control circuitry determines that a signal criterion is met, and controls application of a voltage signal generated by the second voltage regulation circuit to stabilize a voltage signal generated by the first voltage regulation circuit.
    Type: Application
    Filed: July 27, 2022
    Publication date: February 1, 2024
    Inventors: Leon Zlotnik, Leonid Minz, Ekram H. Bhuiyan
  • Patent number: 11888318
    Abstract: Sensing circuitry and clock management circuitry provide transient load management. The sensing circuitry detects a voltage, current, and/or activity associated with a system-on-chip (SoC) and determines whether the detected voltage, current, and/or activity meets a threshold. The clock management circuitry generates clocking signals for the SoC and alters a frequency of the generated clocking signals in response to the detected voltage, current, and/or activity meeting the threshold to alter an amount of power consumed by the SoC.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: January 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Leon Zlotnik, Leonid Minz, Ekram H. Bhuiyan