Abstract: Systems and methods for measuring a curvature radius of a sample. The methods comprise: emitting a light beam from a laser source in a direction towards a beam expander; expanding a size of the light beam emitted from the laser source to create a broad laser beam; reflecting the broad laser beam off of a curved surface of the sample; creating a plurality of non-parallel laser beams by passing the reflected broad laser beam through a grating mask or a biprism; using the plurality of non-parallel laser beams to create an interference pattern at a camera image sensor; capturing a first image by the camera image sensor; and processing the first image by an image processing device to determine the curvature radius of the sample.

Abstract: Systems and methods for measuring a curvature radius of a sample. The methods comprise: emitting a light beam from a laser source in a direction towards a beam expander; expanding a size of the light beam emitted from the laser source to create a broad laser beam; reflecting the broad laser beam off of a curved surface of the sample; creating a plurality of non-parallel laser beams by passing the reflected broad laser beam through a grating mask or a biprism; using the plurality of non-parallel laser beams to create an interference pattern at a camera image sensor; capturing a first image by the camera image sensor; and processing the first image by an image processing device to determine the curvature radius of the sample.

Abstract: Systems and methods for measuring a curvature radius of a sample. The methods comprise: emitting a light beam from a laser source in a direction towards a beam expander; expanding a size of the light beam emitted from the laser source to create a broad laser beam; reflecting the broad laser beam off of a curved surface of the sample; creating a plurality of non-parallel laser beams by passing the reflected broad laser beam through a grating mask or a biprism; using the plurality of non-parallel laser beams to create an interference pattern at a camera image sensor; capturing a first image by the camera image sensor; and processing the first image by an image processing device to determine the curvature radius of the sample.

Abstract: Illustrative embodiments of semiconductor devices including a polar insulation layer capped by a non-polar insulation layer, and methods of fabrication of such semiconductor devices, are disclosed. In at least one illustrative embodiment, a semiconductor device may comprise a semiconductor substrate, a polar insulation layer disposed on the semiconductor substrate and comprising a Group V element configured to increase a carrier mobility in at least a portion of the semiconductor substrate, and a non-polar insulation layer disposed above the polar insulation layer.

Abstract: Illustrative embodiments of semiconductor devices including a polar insulation layer capped by a non-polar insulation layer, and methods of fabrication of such semiconductor devices, are disclosed. In at least one illustrative embodiment, a semiconductor device may comprise a semiconductor substrate, a polar insulation layer disposed on the semiconductor substrate and comprising a Group V element configured to increase a carrier mobility in at least a portion of the semiconductor substrate, and a non-polar insulation layer disposed above the polar insulation layer.

Abstract: Illustrative embodiments of semiconductor devices including a polar insulation layer capped by a non-polar insulation layer, and methods of fabrication of such semiconductor devices, are disclosed. In at least one illustrative embodiment, a semiconductor device may comprise a semiconductor substrate, a polar insulation layer disposed on the semiconductor substrate and comprising a Group V element configured to increase a carrier mobility in at least a portion of the semiconductor substrate, and a non-polar insulation layer disposed above the polar insulation layer.

Abstract: Illustrative embodiments of semiconductor devices including a polar insulation layer capped by a non-polar insulation layer, and methods of fabrication of such semiconductor devices, are disclosed. In at least one illustrative embodiment, a semiconductor device may comprise a semiconductor substrate, a polar insulation layer disposed on the semiconductor substrate and comprising a Group V element configured to increase a carrier mobility in at least a portion of the semiconductor substrate, and a non-polar insulation layer disposed above the polar insulation layer.

Abstract: In one aspect the present invention provides a method for manufacturing a silicon carbide semiconductor device. A layer of silicon dioxide is formed on a silicon carbide substrate and nitrogen is incorporated at the silicon dioxide/silicon carbide interface. In one embodiment, nitrogen is incorporated by annealing the semiconductor device in nitric oxide or nitrous oxide. In another embodiment, nitrogen is incorporated by annealing the semiconductor device in ammonia.

Abstract: In one aspect the present invention provides a method for manufacturing a silicon carbide semiconductor device. A layer of silicon dioxide is formed on a silicon carbide substrate and nitrogen is incorporated at the silicon dioxide/silicon carbide interface. In one embodiment, nitrogen is incorporated by annealing the semiconductor device in nitric oxide or nitrous oxide. In another embodiment, nitrogen is incorporated by annealing the semiconductor device in ammonia. In another aspect, the present invention provides a silicon carbide semiconductor device that has a 4H-silicon carbide substrate, a layer of silicon dioxide disposed on the 4H-silicon carbide substrate and a region of substantial nitrogen concentration at the silicon dioxide/silicon carbide interface.

Abstract: In one aspect the present invention provides a method for manufacturing a silicon carbide semiconductor device. A layer of silicon dioxide is formed on a silicon carbide substrate and nitrogen is incorporated at the silicon dioxide/silicon carbide interface. In one embodiment, nitrogen is incorporated by annealing the semiconductor device in nitric oxide or nitrous oxide. In another embodiment, nitrogen is incorporated by annealing the semiconductor device in ammonia. In another aspect, the present invention provides a silicon carbide semiconductor device that has a 4H-silicon carbide substrate, a layer of silicon dioxide disposed on the 4H-silicon carbide substrate and a region of substantial nitrogen concentration at the silicon dioxide/silicon carbide interface.

Abstract: A method for manufacturing a silicon carbide semiconductor device. In one embodiment, the method includes the following steps: a layer of silicon dioxide is formed on a silicon carbide substrate to create a silicon dioxide/silicon carbide interface and then nitrogen is incorporated at the silicon dioxide/silicon carbide interface for reduction in an interface trap density. The silicon carbide substrate, in one embodiment, includes a n-type 4H-silicon carbide.

Abstract: A new method to fabricate strain patterns on a strained semiconductor structure, is disclosed. The method is based on the new concept of reverse side etching of a laterally homogeneous, strained structure so that strain changes can be induced in the front-side, pre-strained area as a result of the reverse side etching process. Semiconductor structures such as quantum-wires, quantum dots, and quantum well devices may be formed by the disclosed methods where the reverse side etching provides strain control of the material properties of the semiconductor structure without processing the front side which is generally the active and the most sensitive region of the semiconductor structure. Such semiconductor structures can be formed by a process including the steps of forming a strained layer on the front-side of the structure, and etching the reverse side of the substrate to form a pattern of strain into the front-side, thus forming selectively strained regions.

Abstract: A process for making a MOS device on a silicon substrate includes the step of forming a buried layer of germanium-silicon alloy in the substrate, or, alternatively, a buried layer of silicon enclosed between thin, germanium-rich layers. This buried layer is doped with boron, and tends to confine the boron during annealing and oxidation steps. The process includes a step of exposing the substrate to an oxidizing atmosphere such that an oxide layer 10 .ANG.-500 .ANG. thick is grown on the substrate.

Abstract: A graphite path is formed along the surface of a diamond plate, preferably a CVD diamond plate, by means of a laser or ion-implantation induced conductivity. The path advantageously can be the surface of a sidewall of a via hole drilled by the laser through the plate or a path running along a side surface of the plate from top to bottom opposed major surfaces of the plate. The graphite path is metallized, as by electroplating or electroless plating. In this way, for example, an electrically conducting connection can be made between a metallized backplane located on the bottom surface of the plate and a wire-bonding pad located on the top surface of the plate.

Abstract: It has been found that selective metallization in integrated circuits is expeditiously achieved through a copper plating procedure. In this process, palladium silicide is used as a catalytic surface and an electroless plating bath is employed to introduce copper plating only in regions where the silicide is present. Use of this procedure yields superior filling of vias and windows with excellent conductivity.

Abstract: This invention embodies an optical device with a Fabry-Perot cavity formed by two reflective mirrors and an active layer which is doped with a rare earth element selected from lanthanide series elements with number 57 through 71. The thickness of the active layer being a whole number multiple of .lambda./2 wherein .lambda. is the operating, or emissive, wavelength of the device, said whole number being one of the numbers ranging from 1 to 5, the fundamental mode of the cavity being in resonance with the emission wavelength of said selected rare earth element. Cavity-quality factors exceeding Q=300 and finesses of 73 are achieved with structures consisting of two Si/SiO.sub.2 distributed Bragg reflector (DBR) mirrors and an Er-implanted (.lambda./2) SiO.sub.2 active region. The bottom DBR mirror consists of four pairs and the upper DBR mirror consists of two-and-a half pairs of quarterwave (.lambda./4) layers of Si and SiO.sub.2.

Abstract: This invention is a semiconductor vertical cavity surface emitting laser comprising a lasing cavity with an active layer, a bottom (rear) mirror and a top (front) mirror, and a front and rear electrodes for applying excitation current in direction substantially parallel to the direction of optical propagation. In accordance with this invention the front mirror comprises a thin, semitransparent metal layer which also acts as the front electrode. The metal layer is upon a highly doped layer forming a non-alloyed ohmic contact. The metal is selected from Ag and Al and is deposited in thickness ranging from 5 to 55 nm. The VCSEL is a semiconductor device wherein the semiconductor material is a III-V or II-VI compound semiconductor. For a VCSEL with GaAs active layer, the light output from the front metal mirror/electrode side yields a high external differential quantum efficiency as high as 54 percent. This is the highest quantum efficiency obtained in VCSEL structures.

Abstract: A molecular beam epitaxy method of growing Ge.sub.x Si.sub.1-x films on silicon substrate is described. Semiconductor heterostructures using Ge.sub.x Si.sub.1-x layers grown on either Ge or Si substrates are described.

Abstract: A molecular beam epitaxy method of growing Ge.sub.x Si.sub.1-x films on silicon substrate is described.

Abstract: Helium-3 and helium-4 bombardment of InP over a fluence range of 10.sup.11 to 10.sup.16 ions/cm.sup.2 reproducibly forms highly resistive regions in both p-type and n-type single crystal material. Average peak resistivities are about 10.sup.9 ohm-cm for p-type InP and are about 10.sup.3 ohm-cm for n-type InP. High resistivity has also been produced in GaP, GaSb, GaAs, and InGaAs by helium bombardment. Stripe geometry lasers and planar photodiodes which incorporate helium-bombarded zones are described.