Abstract: A source clock system clock domain is selected by communication of the desired clock domain from a receiver clock system through a clock line, such as through a clock differential pair. For instance, the source clock system signals available clock domains by selectively altering the polarity of a first clock line of the pair and the receiver clock system selects from the available clock domains by altering the polarity of a second clock line of the pair. Polarity is altered by selectively interfacing a resistor with the clock lines and then removing the resistor interface when the clock signal associated with the selected clock domain is sent by the source clock system.

Abstract: A source clock system clock domain is selected by communication of the desired clock domain from a receiver clock system through a clock line, such as through a clock differential pair. For instance, the source clock system signals available clock domains by selectively altering the polarity of a first clock line of the pair and the receiver clock system selects from the available clock domains by altering the polarity of a second clock line of the pair. Polarity is altered by selectively interfacing a resistor with the clock lines and then removing the resistor interface when the clock signal associated with the selected clock domain is sent by the source clock system.

Abstract: An information handling system includes a computer system having at least one integrated circuit formed on a die. The integrated circuit includes an output circuit and a device pin operably connected with the output circuit. A load resistor (or other type of load or termination component) and a test switch for selectively connecting the load resistor to the output circuit are also formed on the die. In one aspect, the load resistor is selected to correspond with a representative system load.

Abstract: An information handling system includes a computer system having at least one integrated circuit formed on a die. The integrated circuit includes an output circuit and a device pin operably connected with the output circuit. A load resistor (or other type of load or termination component) and a test switch for selectively connecting the load resistor to the output circuit are also formed on the die. In one aspect, the load resistor is selected to correspond with a representative system load.