Patents by Inventor Leonard F. Roman

Leonard F. Roman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4053924
    Abstract: A semiconductor abrupt junction having a relatively heavily doped region of first conductivity type, a relatively lightly doped region of opposite conductivity type, and immediately adjacent the effective junction, a thin "recombination layer" of first conductivity type and of dopant concentration intermediate that of the two junction regions. Preferably, the recombination layer overlaps the forward biased depletion region of the junction and has a thickness (typically 50 A to 200 A) much less than that of the junction depletion region under reverse bias. The recombination layer dopant ions thereby provide recombination-generation centers only where beneficial to improve the forward and reverse recovery times of the junction without degrading the steady state reverse current characteristics thereof. By further utilizing a very shallow (less than about 800 A) heavily doped region, very low forward turn-on voltage is achieved. The junction may be fabricated by controlled implantation of dopant ions.
    Type: Grant
    Filed: August 2, 1976
    Date of Patent: October 11, 1977
    Assignee: California Linear Circuits, Inc.
    Inventors: Leonard F. Roman, George H. Elliott
  • Patent number: 4035670
    Abstract: The on-to-off switching time of a junction transistor is reduced by forward connecting a recombination layer diode between the base and collector of the transistor. Preferably, the diode comprises a semiconductor abrupt junction of the type having a relatively heavily doped region of first conductivity type, a relatively lightly doped region of opposite conductivity type, and immediately adjacent the effective junction, a thin "recombination layer" of a carrier recombination-generation type material with a dopant concentration intermediate that of the two junction regions. Such a diode exhibits very low forward turn-on voltage and fast forward and reverse recovery times. The diode functions to bypass base-collector toward current of the transistor so as to reduce excess stored charge at the transistor collector-base junction, thereby effectively eliminating the storage delay time typically associated with junction transistor turn-off.
    Type: Grant
    Filed: December 24, 1975
    Date of Patent: July 12, 1977
    Assignee: California Linear Circuits, Inc.
    Inventor: Leonard F. Roman