Patents by Inventor LEONARD GULER

LEONARD GULER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12369393
    Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up approach, are described. For example, integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. The first vertical arrangement of nanowires has a greater number of nanowires than the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has an uppermost nanowire co-planar with an uppermost nanowire of the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has a bottommost nanowire below a bottommost nanowire of the second vertical arrangement of nanowires. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires.
    Type: Grant
    Filed: April 2, 2024
    Date of Patent: July 22, 2025
    Assignee: Intel Corporation
    Inventors: Dax M. Crum, Biswajeet Guha, Leonard Guler, Tahir Ghani
  • Publication number: 20250176225
    Abstract: Fin trim plug structures for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls. The fin has a trench separating a first fin portion and a second fin portion. A first gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the first fin portion. A second gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the second fin portion. An isolation structure is in the trench of the fin, the isolation structure between the first gate structure and the second gate structure. The isolation structure includes a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material, the recessed second dielectric material laterally surrounding an oxidation catalyst layer.
    Type: Application
    Filed: November 23, 2022
    Publication date: May 29, 2025
    Inventors: Leonard GULER, Nick LINDERT, Biswajeet GUHA, Swaminathan SIVAKUMAR, Tahir GHANI
  • Publication number: 20250113564
    Abstract: An integrated circuit (IC) device has a stack of nanoribbons between epitaxial source and drain structures with first and second dielectric sections separated by a dielectric layer and adjacent an epitaxial structure. A second dielectric layer may separate a third dielectric section. The dielectric layers may be conformally between the epitaxial structure and the dielectric sections. A height at a top of the epitaxial structure may be reduced, for example, to be very close to a height at a top of the stack of nanoribbons, e.g., within a pitch or thickness of the nanoribbons.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Leonard Guler, Charles H. Wallace
  • Publication number: 20250113580
    Abstract: Devices, transistor structures, systems, and techniques are described herein related to contacting source and drain transistor structures from the device backside at small dimensions and cell sizes. A first subset of dummy contact structures are removed and backfilled with contact metal and a first etch stop material. A second subset of dummy contact structures are removed and backfilled with contact metal and a second etch stop material. Subsequent metallization contacts to the first and second contacts are made using two masking/selective etch processes such that any misalignment to the other contact type does not allow contact due to the pertinent etch stop material.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Leonard Guler, Shaun Mills, Joseph D'Silva, Ehren Mannebach, Mauro Kobrinsky, Charles H. Wallace, Kalpesh Mahajan, Vivek Vishwakarma, Dincer Unluer, Jessica Panella
  • Publication number: 20250113563
    Abstract: In one embodiment, an integrated circuit structure includes a first transistor device comprising a first gate stack and a second transistor device comprising a second gate stack. The second transistor device is spaced a first distance laterally from the first transistor device. The structure further includes a dielectric region between the first gate stack and the second gate stack. The dielectric region is spaced a second distance laterally from the first transistor device, where the first distance is substantially twice the second distance.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Leonard Guler, Saurabh Acharya, Nidhi Khandelwal, Prabhjot Kaur Luthra, Sean Pursel, Izabela Anna Samek
  • Publication number: 20240404917
    Abstract: Devices, transistor structures, systems, and techniques are described herein related to coupling backside and frontside metallization layers that are on opposite sides of a device layer. A device includes a transistor having semiconductor structures extending between a source and a drain, and a gate between the source and drain, a bridge via extending between a frontside metallization over the transistor and a backside metallization below the transistor, and a thin insulative liner between the bridge via and components of the transistor.
    Type: Application
    Filed: June 1, 2023
    Publication date: December 5, 2024
    Applicant: Intel Corporation
    Inventors: Sikandar Abbas, Chanaka Munasinghe, Leonard Guler, Reza Bayati, Madeleine Stolt, Makram Abd El Qader, Pratik Patel, Anindya Dasgupta
  • Patent number: 12131991
    Abstract: An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: October 29, 2024
    Assignee: Intel Corporation
    Inventors: Manish Chandhok, Leonard Guler, Paul Nyhus, Gobind Bisht, Jonathan Laib, David Shykind, Gurpreet Singh, Eungnak Han, Noriyuki Sato, Charles Wallace, Jinnie Aloysius
  • Publication number: 20240347595
    Abstract: A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.
    Type: Application
    Filed: January 11, 2024
    Publication date: October 17, 2024
    Inventors: William HSU, Biswajeet GUHA, Leonard GULER, Souvik CHAKRABARTY, Jun Sung KANG, Bruce BEATTIE, Tahir GHANI
  • Publication number: 20240332290
    Abstract: Transistor structures comprising a gate electrode, or “gate,” that is self-aligned to underlying channel material. A mask material employed for patterning the channel material is further employed to define a cap of mask material having a larger width that protects a portion of gate material during a gate etch. The cap is therefore self-aligned to the channel material so that an amount by which a gate material extends laterally beyond the channel material is ensured to be symmetrical about a centerline of the channel material.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Applicant: Intel Corporation
    Inventors: Shao-Ming Koh, Patrick Morrow, Nikhil Mehta, Leonard Guler, Sudipto Naskar, Alison Davis, Dan Lavric, Matthew Prince, Jeanne Luce, Charles Wallace, Cortnie Vogelsberg, Rajaram Pai, Caitlin Kilroy, Jojo Amonoo, Sean Pursel, Yulia Gotlib
  • Publication number: 20240266353
    Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up approach, are described. For example, integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. The first vertical arrangement of nanowires has a greater number of nanowires than the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has an uppermost nanowire co-planar with an uppermost nanowire of the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has a bottommost nanowire below a bottommost nanowire of the second vertical arrangement of nanowires. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires.
    Type: Application
    Filed: April 2, 2024
    Publication date: August 8, 2024
    Inventors: Dax M. CRUM, Biswajeet GUHA, Leonard GULER, Tahir GHANI
  • Publication number: 20240241446
    Abstract: Apparatus and methods are disclosed. An example lithography apparatus includes an ultraviolet (UV) source to expose a photoresist layer to UV light; and an extreme ultraviolet (EUV) source coupled to the UV source, the EUV source to expose the photoresist layer to EUV light to via a photomask, a combination of the UV light and the EUV light provide a pattern on the photoresist layer when a developer solution is applied to the photoresist layer.
    Type: Application
    Filed: March 28, 2024
    Publication date: July 18, 2024
    Inventors: Marvin Paik, Charles H. Wallace, Leonard Guler, Elliot N. Tan, Shengsi Liu, Vivek Vishwakarma, Izabela Samek, Mohammadreza Soleymaniha
  • Patent number: 12002810
    Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up approach, are described. For example, integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. The first vertical arrangement of nanowires has a greater number of nanowires than the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has an uppermost nanowire co-planar with an uppermost nanowire of the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has a bottommost nanowire below a bottommost nanowire of the second vertical arrangement of nanowires. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 4, 2024
    Assignee: Intel Corporation
    Inventors: Dax M. Crum, Biswajeet Guha, Leonard Guler, Tahir Ghani
  • Publication number: 20240145598
    Abstract: Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-k”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Inventors: Bruce E. BEATTIE, Leonard GULER, Biswajeet GUHA, Jun Sung KANG, William HSU
  • Patent number: 11929396
    Abstract: A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: William Hsu, Biswajeet Guha, Leonard Guler, Souvik Chakrabarty, Jun Sung Kang, Bruce Beattie, Tahir Ghani
  • Patent number: 11901458
    Abstract: Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-k”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Bruce E. Beattie, Leonard Guler, Biswajeet Guha, Jun Sung Kang, William Hsu
  • Publication number: 20230320057
    Abstract: Integrated circuit (IC) devices include transistors with gate, source and drain contact metallization, some of which are jumpered together by a metallization that is recessed below a height of other metallization that is not jumpered. The jumper metallization may provide a local interconnect between terminals of one transistor or adjacent transistors, for example between a gate of one transistor and a source/drain of another transistor. The jumper metallization may not induce the same pitch constraints faced by interconnect line metallization levels employed for more general interconnection. In some examples, a static random-access memory (SRAM) bit-cell includes a jumper metallization joining two transistors of the cell to reduce cell height for a given feature patterning capability.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 5, 2023
    Applicant: Intel Corporation
    Inventors: Clifford Ong, Leonard Guler, Mohit Haran, Smita Shridharan, Reken Patel, Charles Wallace, Chanaka Munasinghe, Pratik Patel
  • Publication number: 20230209797
    Abstract: Integrated circuit (IC) static random-access memory (SRAM) comprising colinear pass-gate transistors and pull-down transistors having different nanoribbon widths. A narrower ribbon width within the pass-gate transistor, relative to the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a transition between narrower and width ribbon widths is symmetrical about a centerline shared by ribbons of both the access and pull-down transistors. In some examples, the ribbon width transition is positioned within an impurity-doped semiconductor region shared by the access and pull-down transistors and may be located under a terminal contact metallization. In some examples, the impurity-doped semiconductor regions surrounding the ribbons of differing width also have differing widths.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Applicant: Intel Corporation
    Inventors: Clifford Ong, Leonard Guler, Smita Shridharan, Zheng Guo, Eric Karl, Tahir Ghani
  • Publication number: 20230209798
    Abstract: Integrated circuit (IC) static random-access memory (SRAM) bit-cell structures comprising pass-gate transistors having a different number of active channel regions than the number of active channel regions in pull-down transistors. A pass-gate transistor with fewer active channel regions than a pull-down transistor may reduce read instability of an SRAM bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, one or more pass-gate transistor channel regions are impurity doped or removed from either a top side or bottom side of the pass-gate transistors to depopulate the number of active channel regions relative to a pull-down transistor.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Applicant: Intel Corporation
    Inventors: Clifford Ong, Leonard Guler, Mohammad Hasan, Tahir Ghani
  • Publication number: 20230209799
    Abstract: Integrated circuit (IC) static random-access memory (SRAM) comprising pass-gate transistors and pull-down transistors having different threshold voltages (Vt). A pass-gate transistor with a higher Vt than the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a different amount of a dipole dopant source material is deposited as part of the gate insulator for the pull-down transistor than for the pass-gate transistor, reducing the Vt of the pull-down transistor accordingly. In some examples, an N-dipole dopant source material is removed from the pass-gate transistor prior to a drive/activation anneal is performed. After drive/activation, the N-dipole dopant source material may be removed from the pull-down transistor and a same gate metal deposited over both the pass-gate and pull-down transistors.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Applicant: Intel Corporation
    Inventors: Clifford Ong, Dan Lavric, Leonard Guler, YenTing Chiu, Smita Shridharan, Zheng Guo, Eric A. Karl, Tahir Ghani
  • Publication number: 20230114214
    Abstract: Single-sided nanosheet transistor structures comprising an upper channel material over a lower channel material. A first dielectric material is formed adjacent to a first sidewall of the upper and lower channel materials. A second dielectric material is formed adjacent to a second sidewall of the upper and lower channel materials. The first sidewall of the upper and lower channel materials is exposed by etching at least a portion of the first dielectric material. A sidewall portion of the second dielectric material may be exposed by removing sacrificial material from between the upper and lower channel materials. A single-sided gate stack may then be formed in direct contact with the first sidewall of the upper and lower channel materials, and in contact with the sidewall portion of the second dielectric material.
    Type: Application
    Filed: September 24, 2021
    Publication date: April 13, 2023
    Applicant: Intel Corporation
    Inventors: Stephen Cea, Biswajeet Guha, Leonard Guler, Tahir Ghani, Sean Ma