Abstract: A matched pair of npn transistor configured as emitter followers provide high impedance isolation for input error voltage busses in the current share circuitry used with parallel connected current programmed dc to dc converters. The matched emitter followers offer the bus isolation of buffer amplifiers but do not add the detrimental offset voltage to the input error signals. Trimmable current sinks are connected to the emitters of the transistors to guarantee equal VBE drops. Slight intentional unbalancing can be introduced using the current sources to improve stability. The current share circuitry equalizes main FET switching currents not load currents reducing FET stresses. A programmable differential amplifier is provided which can accommodate different regulator output voltages. Diagnostic circuitry monitors share circuitry operation.

Abstract: A circuit for producing one or more regulated auxiliary voltages from a single zero-volt full bridge power stage without degrading the zero-volt switching action. The freewheeling diode used in previous magnetic amplifiers is no longer needed. Transformer current is carried to an auxiliary output inductor through a gate winding of a saturable reactor while a second saturable reactor is reset. Current from the output inductor normally diverted through the freewheeling diode is provided to the transformer through the first saturable reactor just before the transformer provides a pulse of opposite polarity thus discharging the capacitance of the primary switches and enhancing the full bridge zero-volt switching process.

Abstract: The present invention is a circuit and method for reducing switching losses in a full bridge, resonant transition, switching power converter. The converter circuit includes a bridge switching circuit having an FET switch in each leg of the bridge. Each FET has a parasitic drain-to-source capacitance. The primary of a power transformer is connected across the bridge. Two secondary windings of the transformer are connected in a center-tapped configuration. A saturable reactor and a rectifier is connected in series with each secondary winding. A control means controls the conduction interval of the FET switches to produce a first and a second half-cycle of converter operation, each half-cycle including an on-time and a free-wheeling interval. The saturable reactors force unequal current distribution in the secondary windings during the free-wheeling intervals such that a primary current is caused to flow.

Abstract: A full bridge non-resonant switching circuit is disclosed which has an inductive device and four switches. Parasitic controlling mechanisms are operatively connected to the four switches to control inductive energy release in order to switch current through the switches at substantially zero voltage.