Abstract: Apparatus for detecting the presence of a speed detection system includes a microcontroller, a laser detector circuit coupled to the microcontroller, a radar detector circuit coupled to the microcontroller and a display coupled to the microcontroller, wherein the microcontroller receives signals from the laser detector and radar detector circuits and in response to the signals fed thereto, the microcontroller provides an output signal indicating which of the laser and radar detector circuits fed a signal thereto.

Abstract: A digital processing system includes first and second processors and first and second random access memories (RAMs) respectively associated with the first and second processors. Each of the first and second RAMs includes a plurality of independent memory cells, each cell in the first RAM having associated therewith a corresponding cell in the second RAM. Input/output circuitry provides independent access by the first processor to the first RAM and by the second processor to the second RAM. Control logic is responsive to a transfer control signal to simultaneously transfer data stored in the memory cells of one of the first and second RAMs into the corresponding cells of the other of the first and second RAMs. Data may be selectively transferred such that only data stored in selected memory cells is transferred between the first and second RAMs.

Abstract: Memory apparatus for simultaneously transferring data between corresponding memory cells of two RAMs is disclosed. The two memories are fabricated on a common integrated circuit chip substrate with the corresponding memory cells of the two memories positioned adjacent one another and interconnected through a pair of transfer transistors. The transfer transistors as well as the power supply to each memory cell are controllable to cause the simultaneous copying of the data from the cells of one RAM into the corresponding cells of the other RAM.

Abstract: Memory apparatus for simultaneously transferring data between corresponding memory cells of two RAMs is disclosed. The two memories are fabricated on a common integrated circuit chip substrate with the corresponding memory cells of the two memories positioned adjacent one another and interconnected through a pair of transfer transistors. The transfer transistors as well as the power supply to each memory cell are controllable to cause the simultaneous copying of the data from the cells of one RAM into the corresponding cells of the other RAM.