Abstract: A die package generally including (A) ground paths routing a power ground from a ground power set of contact pads in a first conductive layer to a ground ring in a second conductive layer, (B) core paths routing a core voltage from a core power set of contact pads in the first conductive layer to a core ring in the second conductive layer, and (C) input/output voltage paths routing input/output voltages from an input/output power set of contact pads in the first conductive layer to an input/output ring in the second conductive layer, (i) the input/output ring surrounding the core ring, (ii) the ring being configured to power input and output circuits of the die, (iii) the input/output ring being split into ring segments isolated from each other and (iv) at least one particular ring segment having a length of less than a single connector pitch.

Abstract: A die package generally including (A) ground paths routing a power ground from a ground power set of contact pads in a first conductive layer to a ground ring in a second conductive layer, (B) core paths routing a core voltage from a core power set of contact pads in the first conductive layer to a core ring in the second conductive layer, and (C) input/output voltage paths routing input/output voltages from an input/output power set of contact pads in the first conductive layer to an input/output ring in the second conductive layer, (i) the input/output ring surrounding the core ring, (ii) the ring being configured to power input and output circuits of the die, (iii) the input/output ring being split into ring segments isolated from each other and (iv) at least one particular ring segment having a length of less than a single connector pitch.

Abstract: A semiconductor substrate having high density signal routing is provided. The semiconductor substrate may include first signal traces electrically connected to a first row of signal bonding pads and routed on a first layer of the substrate. In addition, the substrate may include second signal traces electrically connected to a second row of signal bonding pads and routed on a second layer of the substrate. The first layer may be arranged in a strip line configuration, and the second layer may be arranged in a micro strip line configuration. Alternatively, the second signal traces may be arranged in a strip line configuration. In an embodiment, the first and second signal traces may be routed as differential pairs with approximately equal trace lengths. In another embodiment, all of the first and second signal traces may be routed as differential pairs.

Abstract: A semiconductor substrate having multiple signal voltage power supplies is provided. The substrate may include a signal voltage power ring separated into segmented voltage supply connections laterally spaced across the upper surface of the substrate. In addition, the substrate may include a voltage supply plane formed within the substrate. The voltage supply plane may be separated into segmented planes. Vias may electrically connect the segmented voltage supply connections to the segmented planes. In an embodiment, at least 2 of the segmented planes may have different voltage supplies. For example, each of the segmented voltage supply connections are configurable to supply power to a portion of input/output drivers of an integrated circuit. Voltage supplies of the segmented planes may be determined based on voltage requirements of the portions of the input/output drivers.

Abstract: A substrate of the type for receiving an integrated circuit and a mold cover. The mold cover covers a first portion of the substrate and leaves a second portion of the substrate exposed with a boundary edge between the first portion of the substrate and a second portion of the substrate. The substrate has electrically conductive traces and electrically conductive vias on an upper layer adjacent the mold cover. The electrically conductive traces do not cross the boundary edge on the upper layer of the substrate.

Abstract: A substrate of the type for receiving an integrated circuit and a mold cover. The mold cover covers a first portion of the substrate and leaves a second portion of the substrate exposed with a boundary edge between the first portion of the substrate and a second portion of the substrate. The substrate has electrically conductive traces and electrically conductive vias on an upper layer adjacent the mold cover. The electrically conductive traces do not cross the boundary edge on the upper layer of the substrate.

Abstract: A substrate for electrically connecting to an integrated circuit, where the integrated circuit has differential pairs of signals that are associated with differential pairs of integrated circuit contacts. Differential pairs of substrate contacts are disposed on a first substrate layer in alignment with the differential pairs of integrated circuit contacts. Differential pairs of vias are also disposed on the first substrate layer, and extend to at least one underlying substrate layer. The differential pairs of vias make electrical connections with the differential pairs of substrate contacts. Each via within a given one of the differential pairs of vias is disposed within a column with each other on the first substrate layer. The columns for each of the differential pairs of vias are in a substantially parallel arrangement one with another. Differential pairs of traces are disposed on the at least one underlying substrate layer.

Abstract: One or more reinforcement pins are inserted between the lid and base of a sealed integrated-circuit package. The reinforcement pins reinforce a sealing layer between the lid and the base, particularly against shear forces exerted on the sealing layer between the lid and the base of a package. Shorter pins are provided which do not extend through the lid or base. Longer pins are provided which extend through the lid or base, with the ends of the pins being mechanically secured to the lid or base and sealed with solder, glass, or epoxy material.

Abstract: A package for an integrated-circuit includes a package body having a die-cavity formed therein. A die-attach pad is formed in the package body adjacent the die-cavity. An opening is formed in the central portion of the die-attach pad for exposing one side of the integrated-circuit die so that an external cooling media can directly contact the exposed side of the integrated-circuit die. The die-attach pad can be formed as a die-mounting ring adjacent the die-attach cavity. The peripheral edge of the integrated-circuit die is fixed to a mounting surface on the die-mounting ring portion to accommodate direct cooling of the exposed side of the integrated-circuit die. The mounting surface of the die-mounting ring extends beyond the peripheral edge of the integrated-circuit die to accommodate a range of sizes of the integrated-circuit die.