Patents by Inventor Leonard Link

Leonard Link has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8085700
    Abstract: A multi-node communications system is provided with communications protocol using both static (11, 12, 13, 18) (pre-determined) and dynamic (51, 52, 53 . . . ) (run-time determined) consecutive communication slots is used. The system has a number of distributed communication nodes, each node being arranged for communicating frames of data with the other nodes during both the static (11, 12, 13 . . . ) and the dynamic (51, 52, 53 . . . ) communication slots. Each node includes a synchronized time base 5 made up of consecutive timeslots (11, 12, 13 . . . , 51, 52, 53 . . . ). The timebase 5 has substantially the same error tolerance in each node. For static communication (10), a predetermined number of timeslots (20) are utilized for each static communication slot. For dynamic communication a dynamically allocated number of timeslots (60) are utilized for each dynamic communication slot. In this way both static and dynamic media arbitration is provided within a periodically recurring communication pattern.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: December 27, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Christopher Temple, Florian Bogenberger, Mathias Rausch, Manfred Thanner, Thomas Wuerz, Leonard Link, Gregor Pokorny
  • Publication number: 20060045133
    Abstract: A multi-node communications system is provided with communications protocol using both static (11, 12, 13, 18) (pre-determined) and dynamic (51, 52, 53 . . . ) (run-time determined) consecutive communication slots is used. The system has a number of distributed communication nodes, each node being arranged for communicating frames of data with the other nodes during both the static (11, 12, 13 . . . ) and the dynamic (51, 52, 53 . . . ) communication slots. Each node includes a synchronized time base 5 made up of consecutive timeslots (11, 12, 13 . . . , 51, 52, 53 . . . ). The timebase 5 has substantially the same error tolerance in each node. For static communication (10), a predetermined number of timeslots (20) are utilized for each static communication slot. For dynamic communication a dynamically allocated number of timeslots (60) are utilized for each dynamic communication slot. In this way both static and dynamic media arbitration is provided within a periodically recurring communication pattern.
    Type: Application
    Filed: November 21, 2003
    Publication date: March 2, 2006
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Christopher Temple, Florian Bogenberger, Mathias Rausch, Manfred Thanner, Thomas Wuerz, Leonard Link
  • Patent number: 6658606
    Abstract: A method for checking an error control unit in a circuit, wherein the error control unit generates an error signal, when operating properly, if the digital circuit is in an error state. The method includes the following steps: invoking the state indicating the error, monitoring the error signal, and generating an alarm signal when the error signal does not appear or appears incorrectly. A device for checking an error control unit of a circuit, wherein the error control unit generates an error signal when it is operating properly if the circuit is in or outputs a state indicating an error, has a device for inducing the state indicating the error, and a device for monitoring the error signal and generating an alarm signal when the error signal does not appear or appears incorrectly after the state indicating the error was induced.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: December 2, 2003
    Assignee: Continental Teves AG & Co. OHG
    Inventors: Leonard Link, Wolfgang Fey