Abstract: A system and method for providing voltage power gating. The system includes a device for providing voltage power gating. The device includes logic circuitry, a mechanism for receiving a control signal associated with the logic circuitry and a selector. The control signal indicates an active state or an idle state of the logic circuitry. The selector enables a power source to the logic circuitry in response to the control signal indicating the active state. The selector also disables the power source to the logic circuitry in response to the control signal indicating the idle state. Thus, the power source is dynamically eliminated from the logic circuitry on the device when it is in the idle state.

Abstract: A system and method for providing voltage power gating. The system includes a device for providing voltage power gating. The device includes logic circuitry, a mechanism for receiving a control signal associated with the logic circuitry and a selector. The control signal indicates an active state or an idle state of the logic circuitry. The selector enables a power source to the logic circuitry in response to the control signal indicating the active state. The selector also disables the power source to the logic circuitry in response to the control signal indicating the idle state. Thus, the power source is dynamically eliminated from the logic circuitry on the device when it is in the idle state.

Abstract: A logical design including multiple logical blocks is mapped onto an integrated circuit chip. A chip level floor plan is created on the chip, including temporary areas on the chip set aside for accommodating logical blocks having logical content including timing requirements based on the logical design. The temporary areas are translated into physical cells on the chip with pins assigned for inputs and outputs for the logical blocks. The logical blocks are mapped to the physical cells on the chip in a time sensitive manner using timing assertions to form temporary logical partitions. Blocks on the chip, including the temporary logical partitions, are connected based on the timing assertions. A timing analysis is performed on the chip to determine timing slack associated with each temporary logical partition. A determination is made whether the timing slack is acceptable.