Abstract: A system for converting an analog signal to a digital signal may include a plurality of converter stages. One of the converter stages may include a multiplying digital-to-analog converter (MDAC) and an analog-to-digital subconverter (ADSC). The MDAC may be configured to (i) receive from a previous stage a first residue analog signal and a first idealized digital signal representing a first portion of the digital signal and corresponding to the first residue analog signal; (ii) convert the first idealized digital signal to an idealized analog signal; and (iii) output a second residue analog signal based on the difference between the first residue analog signal and the idealized analog signal. The ADSC may be configured to convert the second residue analog signal into a second idealized digital signal representing a second portion of the digital signal and corresponding to the second residue analog signal, the ADSC comprising a sloping analog-to-digital converter.

Abstract: A system for converting an analog signal to a digital signal may include a plurality of converter stages. One of the converter stages may include a multiplying digital-to-analog converter (MDAC) and an analog-to-digital subconverter (ADSC). The MDAC may be configured to (i) receive from a previous stage a first residue analog signal and a first idealized digital signal representing a first portion of the digital signal and corresponding to the first residue analog signal; (ii) convert the first idealized digital signal to an idealized analog signal; and (iii) output a second residue analog signal based on the difference between the first residue analog signal and the idealized analog signal. The ADSC may be configured to convert the second residue analog signal into a second idealized digital signal representing a second portion of the digital signal and corresponding to the second residue analog signal, the ADSC comprising a sloping analog-to-digital converter.

Abstract: A method and apparatus for detecting gamma-rays is provided, wherein the gamma-ray detector apparatus includes a plurality of detector elements arranged in a stacked configuration. Each of the plurality of detector elements may include, a detector wafer having at least one anode separated from a cathode via a wafer material, wherein the wafer material includes a wafer material thickness d, and a wafer interface, wherein the wafer interface is electrically connected to the at least one anode.

Abstract: A method and apparatus for detecting gamma-rays is provided, wherein the gamma-ray detector apparatus includes a plurality of detector elements arranged in a stacked configuration. Each of the plurality of detector elements may include, a detector wafer having at least one anode separated from a cathode via a wafer material, wherein the wafer material includes a wafer material thickness d, and a wafer interface, wherein the wafer interface is electrically connected to the at least one anode.

Abstract: A sensor chip assembly time delay integration circuit useful with image sensing arrays uses a duplex bucket brigade circuit (120) with two or more charge transfer paths, a number of capacitors (130, 133, 136) common to the charge transfer paths, and a number of capacitors (131, 132, 134, 135) specific to each of the charge transfer paths. Each of the charge transfer paths has a number of MOSFET transfer gates (122, 124, 126, 128; 123, 125, 127, 129) connected in series, and the common capacitors and the path-specific capacitors are alternately connected to the paths. Each of the common capacitors is controllably connected (112, 115, 118) either to a unit cell input circuit (113, 116, 119). a reset node (111, 114, 117), or an open circuit. The circuit operates by storing accumulated image sensor charges from alternate sensor lines on the path-specific capacitors. The common capacitors are reset and then connected to the unit cell input circuits to acquire a first set of image sensor charges.

Abstract: A time delay integration circuit in which a number of unit cell inputs (101, 103, 105, 107) along with their respective switches (170, 171, 172, 173) are input to a bi-directional BBD circuit (110). The BBD circuit performs an SCA TDI with reduced ROIC circuitry and compatibility with standard LSI processing. The bi-directional BBD circuit has numerous pairs of MOSFETs (111, 112; 113, 114; 115, 116; 117, 118; 119, 120; 121, 122; 123, 124; 125, 126; 127, 128; 129, 130; 131, 132; 133, 134; 135, 136; 137, 138; 139, 140; 141, 142) connected in series and numerous storage capacitors (151, 152,153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166) having one of their terminals respectively connected between each of the MOSFET pairs and the other of their terminals alternately connected to clock phases Ø1 and Ø2.