Abstract: Integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, and methods of fabricating integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the plurality of horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A confined epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A dielectric anchor is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure, the dielectric anchor having an uppermost surface below an uppermost surface of the confined epitaxial source or drain structure.

Abstract: Integrated circuit structures having a dielectric anchor void, and methods of fabricating integrated circuit structures having a dielectric anchor void, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A dielectric anchor is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure. A second portion of the STI structure on a side of the plurality of horizontally stacked nanowires opposite the dielectric anchor has a trench therein. A dielectric gate plug is on the dielectric anchor.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a first interlayer dielectric (ILD), a plurality of source/drain (S/D) contacts in the first ILD, a plurality of gate contacts in the first ILD, wherein the gate contacts and the S/D contacts are arranged in an alternating pattern, and wherein top surfaces of the gate contacts are below top surfaces of the S/D contacts so that a channel defined by sidewall surfaces of the first ILD is positioned over each of the gate contacts, mask layer partially filling a first channel over a first gate contact, and a fill metal filling a second channel over a second gate contact that is adjacent to the first gate contact.

Abstract: Techniques are provided to form semiconductor devices that include a gate cut that passes through a plurality of semiconductor bodies (e.g., nanoribbons or nanosheets) such that the gate cut acts as a dielectric spine in a forksheet arrangement with the semiconductor bodies on either side of the gate cut. In an example, two semiconductor devices in a forksheet arrangement include semiconductor bodies directly on either side of a dielectric spine. A gate structure includes a gate dielectric (e.g., high-k gate dielectric material) and a gate electrode (e.g., conductive material such as workfunction material and/or gate fill metal) that extends around each of the semiconductor bodies of both semiconductor devices. The dielectric spine interrupts the entire height of the gate structure between the two devices and includes dielectric material (e.g., low-k dielectric), and the gate dielectric of the gate structure is not present along sidewalls of the spine between adjacent bodies.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a plug within a metal layer of a semiconductor device, where the plug is formed within a cavity that is created through the metal layer. The plug may extend through the metal layer and into a layer below the metal layer, which may be a layer that includes a dielectric and one or more electrical routing features. The plug may include an electrical insulator material. The cavity may be formed by placing a mask above the metal layer and performing an etch through the metal layer subsequently filled with a dielectric, where the plug will be tapered and wider at the top of the plug and become narrower as the plug continues through the metal layer and reaches the layer below the metal layer. Other embodiments may be described and/or claimed.

Abstract: Integrated circuit structures having fin isolation regions recessed for gate contact are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A dielectric gate cut plug is between the gate structure and the dielectric structure. A recess is in the dielectric structure and in the dielectric gate cut plug. A conductive structure is in the recess, the conductive structure in lateral contact with a gate electrode of the gate structure.

Abstract: An integrated circuit includes a first device having a first source or drain region, and a second device having a second source or drain region that is laterally adjacent to the first source or drain region. A conductive source or drain contact includes (i) a lower portion in contact with the first source or drain region, and extending above the first source or drain region, and (ii) an upper portion extending laterally from above the lower portion to above the second source or drain region. A dielectric material is between at least a section of the upper portion of the conductive source or drain contact and the second source or drain region. In an example, each of the first and second devices is a gate-all-around (GAA) device having one or more nanoribbons, nanowires, or nanosheets as channel regions, or is a finFet structure having a fin-based channel region.

Abstract: An integrated circuit includes a first device and a laterally adjacent second device. The first device includes a first body including semiconductor material extending from a first source region to a first drain region, and a first gate structure on the first body. The second device includes a second body including semiconductor material extending from a second source region to a second drain region, and a second gate structure on the second body. A gate cut including dielectric material is between and laterally separates the first gate structure and the second gate structure. The first body is separated laterally from the gate cut by a first distance, and the second body is separated laterally from the gate cut by a second distance. In an example, the first and second distances differ by at least 2 nanometers. In an example, the first and second devices are fin-based devices or gate-all-around devices.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for techniques for creating a wall within a forkFET transistor structure, where the wall is adjacent to a first stack of nanoribbons on a first side of the wall and a second stack of nanoribbons on a second side of the wall opposite the first side of the wall. In embodiments, the wall extends beyond the top of the first stack of nanoribbons and electrically isolates a first gate metal coupled with the first stack of nanoribbons and a second gate metal coupled with the second stack of nanoribbons from each other. Other embodiments may be described and/or claimed.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for integrated circuit structures that include self-aligned metal gates, self-aligned epitaxial structure, self-aligned terminal contacts over the epitaxial structure, and removal of poly material around a gate during integrated circuit structure manufacture, using a tub gate architecture. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive lines in a first inter-layer dielectric (ILD) layer, the plurality of conductive lines on a same level and along a same direction. A second ILD layer is over the plurality of conductive lines and over the first ILD layer. A first conductive via is in a first opening in the second ILD layer, the first conductive via in contact with a first one of the plurality of conductive lines, the first conductive via having a straight edge.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a plug between two gates within a transistor layer of a semiconductor device. In embodiments, the plug includes a cap at a top of the plug and a liner surrounding at least a portion of the cap, and a base below the cap and the liner. The cap may include a metal. A top of the cap may be even with, or substantially even with, the top of the two gates. The plug may provide a more even surface at a top of a transistor layer where the plug fills in for a gate cut. Other embodiments may be described and/or claimed.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a wall within a metal gate cut in a transistor layer of a semiconductor device, where the wall includes a volume of a gas such as air, nitrogen, or another inert gas. Other embodiments may be described and/or claimed.

Abstract: An integrated circuit includes laterally adjacent first and second devices. The first device includes (i) first source and drain regions, (ii) a first body including semiconductor material laterally extending between the first source and drain regions, (iii) a first sub-fin below the first body, and (iv) a first gate structure on the first body. The second device includes (i) second source and drain regions, (ii) a second body including semiconductor material laterally extending from the second source and drain regions, (iii) a second sub-fin below the second body, and (iv) a second gate structure on the second body. A second dielectric material is laterally between the first and second sub-fins. A third dielectric material is laterally between the first and second sub-fins, and above the second dielectric material. A gate cut including first dielectric material is laterally between the first and second gate structures, and above the third dielectric material.

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive lines along a same direction, one of the conductive lines having a break therein. An inter-layer dielectric (ILD) structure has portions between adjacent ones of the plurality of conductive lines and has a dielectric plug portion in a location of the break in the one of the conductive lines. The dielectric plug portion of the ILD structure is continuous with one or more of the portions of the ILD structure between adjacent ones of the plurality of conductive lines. The dielectric plug portion of the ILD structure has an inwardly tapering profile from top to bottom.

Abstract: Mushroomed via structures for trench contact or gate contact are described. In an example, an integrated circuit structure includes a trench contact structure over an epitaxial source or drain structure. A dielectric layer is over the trench contact structure. A trench contact via is in an opening in the dielectric layer, the trench contact via in contact with the trench contact structure. A trench contact via extension is on the trench contact via. The trench contact via extension above the dielectric layer and extending laterally beyond the trench contact via.

Abstract: Integrated circuit structures having gate volume reduction, and methods of fabricating integrated circuit structures having gate volume reduction, are described. For example, an integrated circuit structure includes a sub-fin structure beneath a stack of nanowires, the stack of nanowires having a first side and a second side. A dielectric backbone structure is along the first side of the stack of nanowires. The dielectric backbone structure has a bottom above a bottom of the sub-fin. A gate electrode is over the stack of nanowires and is along the second side of the stack of nanowires. A gate dielectric structure is between the gate electrode and the stack of nanowires.

Abstract: Integrated circuit structures having channel cap reduction, and methods of fabricating integrated circuit structures having channel cap reduction, are described. For example, an integrated circuit structure includes a sub-fin structure beneath a stack of nanowires, the stack of nanowires having a first end and a second end. A dielectric cap has a first portion vertically over the first end of the stack of nanowires and has a second portion vertically over the second end of the stack of nanowires. The dielectric cap is not vertically over a location between the first end and the second end of the stack of nanowires. A gate electrode is over and around the stack of nanowires and laterally between the first and second portions of the dielectric cap. A gate dielectric structure is between the gate electrode and the stack of nanowires.

Abstract: Integrated circuit structures having fin isolation regions bound by gate cuts are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A gate cut is between the gate structure and the dielectric structure.

Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.