Abstract: A reconfigurable computer system which includes two computer subsystems, corresponding lines of the system busses of the two computer subsystems being interconnected by solid state switches. Each of the computer subsystems includes a control component, a service processor, which when an error is detected that would render the subsystem inoperative, causes the solid state switches to open to sever the connection between the system busses of the two computer subsystems so that the computer subsystem that has not suffered such a failure can continue to operate. A communication link is also established between the two service processors. Either, or both, service processors can sever the link between them.

Abstract: In order to achieve the integration of a plurality of processors, each capable of directly addressing a limited internal space storage range, with a larger external memory space (e.g., a mass memory), the processors are organized into clusters, each having a plurality of processors and a common secondary cache. Each cluster is assigned a two-bit cluster number. Intermediate a primary cache in each processor and the secondary cache in the cluster, an address translator is provided for effecting transformation between internal memory space addresses and external memory space addresses. The external memory space is divided into areas private to each cluster and shared by all the processors. An internal address indicator bit, in conjunction with the cluster number from a requesting processor primary cache, is employed to set up the transformation either to the private external space of that cluster or the shared external space.

Abstract: In order to obtain precise submodel control in a central processing unit, there is provided a subcounter which is controlled to count up from a beginning count as an instruction is executed and to count back down at the same rate to the reference count to obtain an effective delay before processing of the next instruction to be processed during normal program execution is started. Instruction transfer and decoding of the new instruction entering the pipeline is inhibited until the subcounter's most significant bit ("sign bit") changes state. If the subcounter is allowed to count during the entire count up and count down periods, a derated mode of 1/2 is achieved. To obtain other fractions, the subcounter is controlled to count periodically during one count direction period and to count full time during the other count direction period.

Abstract: In order to gather, store temporarily and deliver (if needed) central processor safestore information, a multiphase clock is employed to capture (one full clock cycle behind) the safestore information which typically includes all software visible registers in all (or selected) data manipulation chips of the CPU by routing the safestore information through temporary storage (under the influence of the multiphase clock) in a cache data array and into a special purpose XRAM module. Thus, upon the sensing of a fault, valid safestore information is available in the XRAM for analysis and, if appropriate, resumption of operation at a sequential point just previous to that at which the fault occurred.

Abstract: In order to provide efficient error detection in a central processor's Basic Processing Unit (BPU) including an AX (address and execution) module, a DN (decimal numeric) module and an FP (floating point) module, each module is provided redundantly in a master/slave pair, and the local result of data manipulation operations performed in each pair are compared for identity before the results are validated for subsequent use in the central processor.

Abstract: Lock-out of pending higher high priority requests to a system controller is prevented by a circuit which comprises a counter element for counting the number of times the pending higher high priority request is not granted access. The counting results in a count value which is temporarily stored in the counter element. A compare element compares the count value to a predetermined value, the predetermined value being a predetermined number of times the data processing system will permit bypassing the pending higher high priority request. A control signal is outputted from the compare element when the count value is equal to the predetermined value and is coupled to each port to inhibit any further request for access from the equipment from being accepted by the system controller.

Abstract: The apparatus controls access to at least one subsystem in response to requests for access from a plurality of equipments operatively connected to a corresponding port of said apparatus. The requests for access have a plurality of command levels wherein the command levels have a fixed predetermined priority relative to each other. The apparatus comprises a plurality of port request control elements for generating a plurality of specific request signals including a command level request signal to indicate the command level of a request received from the corresponding equipment, and a go signal to indicate the availability of the apparatus and the subsystem in order to execute the command requested. An activity priority select control element receives the specific request signals, and processes the go signals from each of the port request control elements to grant access within a predetermined time period to the equipment connected to the port having the highest port priority within the highest command level.

Abstract: The invention comprises circuitry for systematically multiplying two arbitrary field elements in a Galois field GF(2.sup.m). Each element is represented by an m-bit binary number. The multiplicand field element is passed serially through a plurality of m-1 modulo multipliers. The multiplicand and the product from each of the m-1 modulo multipliers are passed through networks which are gated by bits of the multiplier field element forming partial products. The partial products are summed to form the bit representations of the final product.

Abstract: Apparatus for directly decoding and correcting double-bit random errors per word and for detecting triple-bit errors per word is disclosed. Said apparatus comprises a syndrome calculator which operates upon codewords received from memory and generates syndromes. The syndromes are operated upon and translated by a mapping device which generates pointers identifying the bits which are in error. The pointers are then passed through decoding means to generate error words which are summed with the received word from memory to provide a corrected codeword. The syndrome calculator may further provide a parity check signal to determine if a three-bit error is present, in which case the decoding means are not enabled and a signal is generated indicating that a triple-bit error has been detected which is not correctable.