Patents by Inventor Leonard Reeves

Leonard Reeves has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200279830
    Abstract: A redistribution assembly may have multiple layers. Each layer may include a signal conductor and a ground conductor. The width of the ground conductors may exceed the width of the signal conductors. In addition, the layers may be vertically positioned over each other to form the redistribution layer assembly. The conductors may be interleaved such that the ground conductor of a top layer is vertically positioned over the signal conductor for a bottom layer and the signal conductor of the top layer is positioned over the ground conductor of the bottom layer. Multi-layer redistribution layer assemblies may be used with stacks of dies in an IC package to create a fly-by topology that provides electrical continuity in the X, Y and Z dimensions.
    Type: Application
    Filed: February 28, 2019
    Publication date: September 3, 2020
    Inventors: Seann AYERS, Leonard REEVES
  • Publication number: 20050284366
    Abstract: A system for building a TRC includes a spray mechanism for spraying a coating material, a target system including a rotatable spray-target that retains an object with a surface to be covered by the TRC, a temperature sensor, and a control system for controlling application of the coating material based on a temperature that is determined during the spraying. The temperature sensor may comprise a non-contact infrared sensor that may measure a temperature related to the object. The measured temperature may be controlled by varying the speed of the rotatable spray-target.
    Type: Application
    Filed: September 14, 2004
    Publication date: December 29, 2005
    Inventors: Curtis Anderson, Thomas Dowland, Leonard Reeves, Bjarne Heggli
  • Patent number: 5434745
    Abstract: Disclosed is a stacked die carrier assembly and method for packaging and interconnecting silicon chips such as memory chips. The carrier is constructed from a metalized substrate onto which the chip is attached. The chip is wire bonded to the conductor pattern on the substrate. Each conductor then is routed to the edge of the substrate where it is connected to a half-circle of a metalized through hole. A frame is attached on top of this substrate. This frame has also a pattern of half-circle metalized through holes that aligns with the holes on the bottom substrate. The combination of the bottom substrate with the silicon die, and the frame on top, forms a basic stackable unit. Several such units can be stacked and attached on top of each other. The top unit can finally be covered with a ceramic lid that also has a matching half-circle metalized through hole pattern along its edge.
    Type: Grant
    Filed: July 26, 1994
    Date of Patent: July 18, 1995
    Assignee: White Microelectronics Div. of Bowmar Instrument Corp.
    Inventors: Hamid Shokrgozar, Leonard Reeves, Bjarne Heggli