Patents by Inventor Leonardus Henricus Marie Verstappen

Leonardus Henricus Marie Verstappen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11977034
    Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked to at least partially recompose the measurement results according to the sample plan.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: May 7, 2024
    Assignee: ASML Netherlands B.V.
    Inventors: Wouter Lodewijk Elings, Franciscus Bernardus Maria Van Bilsen, Christianus Gerardus Maria De Mol, Everhardus Cornelis Mos, Hoite Pieter Theodoor Tolsma, Peter Ten Berge, Paul Jacques Van Wijnen, Leonardus Henricus Marie Verstappen, Gerald Dicker, Reiner Maria Jungblut, Chung-Hsun Li
  • Publication number: 20230185990
    Abstract: A method including performing a simulation to evaluate a plurality of metrology targets and/or a plurality of metrology recipes used to measure a metrology target, identifying one or more metrology targets and/or metrology recipes from the evaluated plurality of metrology targets and/or metrology recipes, receiving measurement data of the one or more identified metrology targets and/or metrology recipes, and using the measurement data to tune a metrology target parameter or metrology recipe parameter.
    Type: Application
    Filed: January 10, 2023
    Publication date: June 15, 2023
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Lotte Marloes Willems, Kaustuve Bhattacharyya, Panagiotis Pieter Bintevinos, Guangqing Chen, Martin Ebert, Pieter Jacob Mathias Hendrik Knelissen, Stephen Morgan, Maurits Van Der Schaar, Leonardus Henricus Marie Verstappen, Jen-Shiang Wang, Peter Hanzen Wardenier
  • Patent number: 11580274
    Abstract: A method including performing a simulation to evaluate a plurality of metrology targets and/or a plurality of metrology recipes used to measure a metrology target, identifying one or more metrology targets and/or metrology recipes from the evaluated plurality of metrology targets and/or metrology recipes, receiving measurement data of the one or more identified metrology targets and/or metrology recipes, and using the measurement data to tune a metrology target parameter or metrology recipe parameter.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: February 14, 2023
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Lotte Marloes Willems, Kaustuve Bhattacharyya, Panagiotis Pieter Bintevinos, Guangqing Chen, Martin Ebert, Pieter Jacob Mathias Hendrik Knelissen, Stephen Morgan, Maurits Van Der Schaar, Leonardus Henricus Marie Verstappen, Jen-Shiang Wang, Peter Hanzen Wardenier
  • Publication number: 20210215622
    Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked to at least partially recompose the measurement results according to the sample plan.
    Type: Application
    Filed: March 8, 2021
    Publication date: July 15, 2021
    Applicant: ASML Netherlands B.V.
    Inventors: Wouter Lodewijk Elings, Franciscus Bernardus Maria Van Bilsen, Christianus Gerardus Maria De Mol, Everhardus Cornelis Mos, Hoite Pieter Theodoor Tolsma, Peter Ten Berge, Paul Jacques Van Wijnen, Leonardus Henricus Marie Verstappen, Gerald Dicker, Reiner Maria Jungblut, Chung-Hsun Li
  • Patent number: 10996176
    Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked to at least partially recompose the measurement results according to the sample plan.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: May 4, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Wouter Lodewijk Elings, Franciscus Bernardus Maria Van Bilsen, Christianus Gerardus Maria De Mol, Everhardus Cornelis Mos, Hoite Pieter Theodoor Tolsma, Peter Ten Berge, Paul Jacques Van Wijnen, Leonardus Henricus Marie Verstappen, Gerald Dicker, Reiner Maria Jungblut, Chung-Hsun Li
  • Patent number: 10746668
    Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced 2506 defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used 2508 to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked 2510 to at least partially recompose the measurement results according to the sample plan.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: August 18, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Wouter Lodewijk Elings, Franciscus Bernardus Maria Van Bilsen, Christianus Gerardus Maria De Mol, Everhardus Cornelis Mos, Hoite Pieter Theodoor Tolsma, Peter Ten Berge, Paul Jacques Van Wijnen, Leonardus Henricus Marie Verstappen, Gerald Dicker, Reiner Maria Jungblut, Chung-Hsun Li
  • Publication number: 20190301850
    Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced 2506 defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used 2508 to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked 2510 to at least partially recompose the measurement results according to the sample plan.
    Type: Application
    Filed: April 10, 2019
    Publication date: October 3, 2019
    Applicant: ASML Netherlands B.V.
    Inventors: Wouter Lodewijk ELINGS, Franciscus Bernardus Maria Van Bilsen, Christianus Gerardus Maria De Mol, Everhardus Cornelis Mos, Hoite Pieter Theodoor Tolsma, Peter Ten Berge, Paul Jacques Van Wijnen, Leonardus Henricus Marie Verstappen, Gerald Dicker, Reiner Maria Jungblut, Chung-Hsun Li
  • Patent number: 10317191
    Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced 2506 defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used 2508 to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked 2510 to at least partially recompose the measurement results according to the sample plan.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: June 11, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Wouter Lodewijk Elings, Franciscus Bernardus Maria Van Bilsen, Christianus Gerardus Maria De Mol, Everhardus Cornelis Mos, Hoite Pieter Theodoor Tolsma, Peter Ten Berge, Paul Jacques Van Wijnen, Leonardus Henricus Marie Verstappen, Gerald Dicker, Reiner Maria Jungblut, Chung-Hsun Li
  • Patent number: 9798250
    Abstract: A lithographic apparatus including an inspection apparatus can measure the overlay error of a target in a scribelane is measured. The overlay error of the required feature in the chip area may differ from this due to, for example, different responses to the exposure process. A model is used to simulate these differences and thus a more accurate measurement of the overlay error of the feature determined.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: October 24, 2017
    Assignee: ASML Netherlands B.V.
    Inventors: Marcus Adrianus Van De Kerkhof, Leonardus Henricus Marie Verstappen
  • Publication number: 20170160073
    Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced 2506 defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used 2508 to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked 2510 to at least partially recompose the measurement results according to the sample plan.
    Type: Application
    Filed: February 14, 2017
    Publication date: June 8, 2017
    Applicant: ASML Netherlands B.V.
    Inventors: Wouter Lodewijk ELINGS, Franciscus Bernardus Maria VAN BILSEN, Christianus Gerardus Maria DE MOL, Everhardus Cornelis MOS, Hoite Pieter Theodoor TOLSMA, Peter TEN BERGE, Paul Jacques VAN WIJNEN, Leonardus Henricus Marie VERSTAPPEN, Gerald DICKER, Reiner Maria JUNGBLUT, Li CHUNG-HSUN
  • Patent number: 9594029
    Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced (2506) defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used (2508) to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked (2510) to at least partially recompose the measurement results according to the sample plan.
    Type: Grant
    Filed: November 22, 2012
    Date of Patent: March 14, 2017
    Assignee: ASML Netherlands B.V.
    Inventors: Wouter Lodewijk Elings, Franciscus Bernardus Maria Van Bilsen, Christianus Gerardus Maria De Mol, Everhardus Cornelis Mos, Hoite Pieter Theodoor Tolsma, Peter Ten Berge, Paul Jacques Van Wijnen, Leonardus Henricus Marie Verstappen, Gerald Dicker, Reiner Maria Jungblut, Li Chung-Hsun
  • Publication number: 20160377992
    Abstract: A lithographic apparatus including an inspection apparatus can measure the overlay error of a target in a scribelane is measured. The overlay error of the required feature in the chip area may differ from this due to, for example, different responses to the exposure process. A model is used to simulate these differences and thus a more accurate measurement of the overlay error of the feature determined.
    Type: Application
    Filed: September 13, 2016
    Publication date: December 29, 2016
    Applicant: ASML Netherlands B.V.
    Inventors: Marcus Adrianus VAN DE KERKHOF, Leonardus Henricus Marie VERSTAPPEN
  • Publication number: 20160018742
    Abstract: The overlay error of a target in a scribelane is measured. The overlay error of the required feature in the chip area may differ from this due to, for example, different responses to the exposure process. A model is used to simulate these differences and thus a more accurate measurement of the overlay error of the feature determined.
    Type: Application
    Filed: September 28, 2015
    Publication date: January 21, 2016
    Applicant: ASML Netherlands B.V.
    Inventors: Marcus Adrianus VAN DE KERKHOF, Leonardus Henricus Marie VERSTAPPEN
  • Patent number: 9201310
    Abstract: The overlay error of a target in a scribelane is measured. The overlay error of the required feature in the chip area may differ from this due to, for example, different responses to the exposure process. A model is used to simulate these differences and thus a more accurate measurement of the overlay error of the feature determined.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: December 1, 2015
    Assignee: ASML Netherlands B.V.
    Inventors: Marcus Adrianus Van De Kerkhof, Leonardus Henricus Marie Verstappen
  • Publication number: 20140354969
    Abstract: In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced (2506) defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used (2508) to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked (2510) to at least partially recompose the measurement results according to the sample plan.
    Type: Application
    Filed: November 22, 2012
    Publication date: December 4, 2014
    Applicant: ASML Netherlands B.V.
    Inventors: Wouter Lodewijk Elings, Franciscus Bernardus Maria Van Bilsen, Christianus Gerardus Maria De Mol, Everhardus Cornelis Mos, Hoite Pieter Theodoor Tolsma, Peter Ten Berge, Paul Jacques Van Wijnen, Leonardus Henricus Marie Verstappen, Gerald Dicker, Reiner Maria Jungblut, Li Chung-Hsun
  • Patent number: 8749775
    Abstract: A method and apparatus is used for inspection of devices to detect processing faults on semiconductor wafers. The method includes illuminating a strip of a die along a scan path with a moving measurement spot. The method further includes detecting scattered radiation to obtain an angle-resolved spectrum, and comparing the scattering data with a library of reference spectra. Based on the comparison, the method includes determining the presence of a fault of the die at the strip. The illumination and detection are performed along the scan path across a region, such that the scattering data is spatially integrated over the region.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: June 10, 2014
    Assignee: ASML Netherlands B.V.
    Inventors: Leonardus Henricus Marie Verstappen, Arie Jeffrey Den Boef
  • Patent number: 8724087
    Abstract: A scatterometer configured to measure a property of a substrate, includes a radiation source configured to provide a radiation beam; and a detector configured to detect a spectrum of the radiation beam reflected from a target (30) on the surface of the substrate (W) and to produce a measurement signal representative of the spectrum. The apparatus includes a beam shaper (51, 53) interposed in the radiation path between the radiation source and the detector, the beam shaper being configured to adjust the cross section of the beam dependent on the shape and/or size of the target.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: May 13, 2014
    Assignee: ASML Netherlands B.V.
    Inventors: Marcus Adrianus Van De Kerkhof, Antoine Gaston Marie Kiers, Maurits Van Der Schaar, Leonardus Henricus Marie Verstappen, Scott Anderson Middlebrooks, Andreas Fuchs
  • Publication number: 20110200246
    Abstract: The overlay error of a target in a scribelane is measured. The overlay error of the required feature in the chip area may differ from this due to, for example, different responses to the exposure process. A model is used to simulate these differences and thus a more accurate measurement of the overlay error of the feature determined.
    Type: Application
    Filed: July 27, 2009
    Publication date: August 18, 2011
    Inventors: Marcus Adrianus Van De Kerkhof, Leonardus Henricus Marie Verstappen
  • Publication number: 20110141444
    Abstract: A scatterometer configured to measure a property of a substrate, includes a radiation source configured to provide a radiation beam; and a detector configured to detect a spectrum of the radiation beam reflected from a target (30) on the surface of the substrate (W) and to produce a measurement signal representative of the spectrum. The apparatus includes a beam shaper (51, 53) interposed in the radiation path between the radiation source and the detector, the beam shaper being configured to adjust the cross section of the beam dependent on the shape and/or size of the target.
    Type: Application
    Filed: April 8, 2009
    Publication date: June 16, 2011
    Inventors: Marcus Adrianus Van De Kerkhof, Antoine Gaston Marie Kiers, Maurits Van Der Schaar, Leonardus Henricus Marie Verstappen, Scott Anderson Middlebrooks, Andreas Fuchs
  • Publication number: 20110085162
    Abstract: A method and apparatus is used for inspection of devices to detect processing faults on semiconductor wafers. Illuminating a strip of a die along a scan path with a moving measurement spot. Detecting scattered radiation to obtain an angle-resolved spectrum that is spatially integrated over the strip. Comparing the scattering data with a library of reference spectra, obtained by measurement or calculation. Based on the comparison, determining the presence of a fault of the die at the strip. The measurement spot is scanned across the wafer in a scan path trajectory comprising large (constant) velocity portions and the acquisition of the angle-resolved spectrum is taken, and comparisons are done, at full scan speed. If a long acquisition is performed along a strip across the die in the Y direction, then variation in the acquired spectrum resulting from position variation will primarily depend on the X position of the spot.
    Type: Application
    Filed: September 15, 2010
    Publication date: April 14, 2011
    Applicant: ASML Netherlands B.V.
    Inventors: Leonardus Henricus Marie VERSTAPPEN, Arie Jeffrey Den Boef