Patents by Inventor Leonardo Castro
Leonardo Castro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210288647Abstract: A level shifter device comprises a first stage level shifter configured to transform an input signal to a first output signal having a voltage between at least one of a VPS control voltage and a ground or a VDD supply voltage and a VNS control voltage. The level shifter device comprises a second stage level shifter arranged subsequent to the first stage level shifter and configured to transform the first output signal to a second output signal having a voltage between the ground and the VDD supply voltage.Type: ApplicationFiled: March 13, 2020Publication date: September 16, 2021Inventors: Leonardo Castro, Rainer Bartenschlager
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Patent number: 11121712Abstract: A level shifter device comprises a first stage level shifter configured to transform an input signal to a first output signal having a voltage between at least one of a VPS control voltage and a ground or a VDD supply voltage and a VNS control voltage. The level shifter device comprises a second stage level shifter arranged subsequent to the first stage level shifter and configured to transform the first output signal to a second output signal having a voltage between the ground and the VDD supply voltage.Type: GrantFiled: March 13, 2020Date of Patent: September 14, 2021Assignee: INFINEON TECHNOLOGIES AGInventors: Leonardo Castro, Rainer Bartenschlager
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Patent number: 9892765Abstract: According to one embodiment, a circuit is described including a circuit component configured to switch from a first state into a second state including a node whose potential changes by a predetermined voltage when the circuit component switches from the first state into the second state, a line coupled with the node wherein the switching of the circuit component from the first state into the second state draws or injects a predetermined charge from or into the line, a capacitor coupled to the line and a compensation circuit configured to generate a predetermined multiple of the predetermined voltage and to compensate the charge drawn from or injected into the line by driving the capacitor with the multiple of the predetermined voltage.Type: GrantFiled: April 11, 2016Date of Patent: February 13, 2018Assignee: Infineon Technologies AGInventors: Giacomo Curatolo, Leonardo Castro
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Patent number: 9659657Abstract: A semiconductor memory device having a plurality of decoders, wherein each decoder is assigned to a select line, wherein no other decoder is assigned to the select line, each decoder has an output configured to charge the select line to when the decoder is activated and to discharge the select line when said decoder is deactivated. Also, each decoder is configured such that, in case that a first decoder gets deactivated after being activated and a second decoder of the decoders gets activated after being deactivated, the output of the first decoder and the output of the second decoder get connected to a common node for a predefined time interval, so that an electrical charge may be transferred from the select line, to the first decoder is assigned to, to the select line, to which the second decoder is assigned to, before the output of the first decoder gets connected to a reference voltage and the output of the second decoder gets connected to a supply voltage.Type: GrantFiled: December 1, 2015Date of Patent: May 23, 2017Assignee: Infineon Technologies AGInventors: Leonardo Castro, Giacomo Curatolo
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Publication number: 20160300598Abstract: According to one embodiment, a circuit is described including a circuit component configured to switch from a first state into a second state including a node whose potential changes by a predetermined voltage when the circuit component switches from the first state into the second state, a line coupled with the node wherein the switching of the circuit component from the first state into the second state draws or injects a predetermined charge from or into the line, a capacitor coupled to the line and a compensation circuit configured to generate a predetermined multiple of the predetermined voltage and to compensate the charge drawn from or injected into the line by driving the capacitor with the multiple of the predetermined voltage.Type: ApplicationFiled: April 11, 2016Publication date: October 13, 2016Inventors: Giacomo CURATOLO, Leonardo CASTRO
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Publication number: 20160163387Abstract: A semiconductor memory device having a plurality of decoders, wherein each decoder is assigned to a select line, wherein no other decoder is assigned to the select line, each decoder has an output configured to charge the select line to when the decoder is activated and to discharge the select line when said decoder is deactivated. Also, each decoder is configured such that, in case that a first decoder gets deactivated after being activated and a second decoder of the decoders gets activated after being deactivated, the output of the first decoder and the output of the second decoder get connected to a common node for a predefined time interval, so that an electrical charge may be transferred from the select line, to the first decoder is assigned to, to the select line, to which the second decoder is assigned to, before the output of the first decoder gets connected to a reference voltage and the output of the second decoder gets connected to a supply voltage.Type: ApplicationFiled: December 1, 2015Publication date: June 9, 2016Inventors: Leonardo CASTRO, Giacomo CURATOLO
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Patent number: 9251864Abstract: The invention relates to an electronic memory system, and more specifically, to a system for providing voltage supply protection in a memory device, and a method for providing voltage supply protection in a memory device. According to an embodiment, a system for providing voltage supply protection in a memory device is provided, the system including a memory array including a plurality of memory cells arranged in a plurality of groups of memory cells, and a plurality of current limiting elements, wherein each group of memory cells is associated with at least one current limiting element.Type: GrantFiled: September 6, 2012Date of Patent: February 2, 2016Assignee: Infineon Technologies AGInventors: Jan Otterstedt, Wolf Allers, Mihail Jefremow, Edvin Paparisto, Leonardo Castro, Thomas Kern
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Patent number: 9190149Abstract: Embodiments relate to systems and methods including a step of switching between two or more erase operations and/or two or more write operations for erasing of and/or writing to least one memory cell of a nonvolatile memory enabling to select a most suitable erase and/or write operation for a particular erase and/or write operation within the memory.Type: GrantFiled: August 24, 2012Date of Patent: November 17, 2015Assignee: Infineon Technologies AGInventors: Jan Otterstedt, Wolf Allers, Mihail Jefremow, Edvin Paparisto, Leonardo Castro, Christian Peters
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Patent number: 9032140Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system for adaptive bit rate programming of a memory device, and a method for adaptive bit rate programming of a memory device. According to an embodiment, a system for adaptive bit rate programming of a memory device including a plurality of memory cells is provided, wherein the memory cells are configured to be electrically programmable by application of a current supplied by a current source, the system including selection devices for selecting memory cells for programming based on availability of current from the current source.Type: GrantFiled: January 28, 2013Date of Patent: May 12, 2015Assignee: Infineon Technologies AGInventors: Wolf Allers, Jan Otterstedt, Mihail Jefremow, Edvin Paparisto, Leonardo Castro
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Publication number: 20140215124Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system for adaptive bit rate programming of a memory device, and a method for adaptive bit rate programming of a memory device. According to an embodiment, a system for adaptive bit rate programming of a memory device including a plurality of memory cells is provided, wherein the memory cells are configured to be electrically programmable by application of a current supplied by a current source, the system including selection devices for selecting memory cells for programming based on availability of current from the current source.Type: ApplicationFiled: January 28, 2013Publication date: July 31, 2014Applicant: Infineon Technologies AGInventors: Wolf Allers, Jan Otterstedt, Mihail Jefremow, Edvin Paparisto, Leonardo Castro
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Publication number: 20140064011Abstract: The invention relates to an electronic memory system, and more specifically, to a system for providing voltage supply protection in a memory device, and a method for providing voltage supply protection in a memory device. According to an embodiment, a system for providing voltage supply protection in a memory device is provided, the system including a memory array including a plurality of memory cells arranged in a plurality of groups of memory cells, and a plurality of current limiting elements, wherein each group of memory cells is associated with at least one current limiting element.Type: ApplicationFiled: September 6, 2012Publication date: March 6, 2014Applicant: Infineon Technologies AGInventors: Jan Otterstedt, Wolf Allers, Mihail Jefremow, Edvin Paparisto, Leonardo Castro, Thomas Kern
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Publication number: 20140056079Abstract: Embodiments relate to systems and methods including a step of switching between two or more erase operations and/or two or more write operations for erasing of and/or writing to least one memory cell of a nonvolatile memory enabling to select a most suitable erase and/or write operation for a particular erase and/or write operation within the memory.Type: ApplicationFiled: August 24, 2012Publication date: February 27, 2014Applicant: Infineon Technologies AGInventors: Jan Otterstedt, Wolf Allers, Mihail Jefremow, Edvin Paparisto, Leonardo Castro, Christian Peters