Patents by Inventor Leonardo Kiyosi Bogaz MITSUYUKI

Leonardo Kiyosi Bogaz MITSUYUKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11467613
    Abstract: An adaptable LDO regulator includes an error amplifier providing an error voltage according to a difference between a feedback voltage and a reference voltage, first and second pass transistors each having a first current electrode for receiving an input voltage, a control electrode for receiving the error voltage, and a second current electrode, the second current electrode of the second pass transistor providing an output voltage, a voltage divider generating the feedback voltage in response to a voltage on an input thereof, and a mode selection network that in a closed loop mode, couples the second current electrodes of the first and second pass transistors together and to the input of the voltage divider, and in an open loop mode, couples the second current electrode of the first pass transistor to the input of the voltage divider and decouples the second current electrodes of the first and second pass transistors.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: October 11, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Kyle Zukowski, Leonardo Kiyosi Bogaz Mitsuyuki, Didier Margairaz
  • Publication number: 20220019253
    Abstract: An adaptable LDO regulator includes an error amplifier providing an error voltage according to a difference between a feedback voltage and a reference voltage, first and second pass transistors each having a first current electrode for receiving an input voltage, a control electrode for receiving the error voltage, and a second current electrode, the second current electrode of the second pass transistor providing an output voltage, a voltage divider generating the feedback voltage in response to a voltage on an input thereof, and a mode selection network that in a closed loop mode, couples the second current electrodes of the first and second pass transistors together and to the input of the voltage divider, and in an open loop mode, couples the second current electrode of the first pass transistor to the input of the voltage divider and decouples the second current electrodes of the first and second pass transistors.
    Type: Application
    Filed: October 21, 2020
    Publication date: January 20, 2022
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Kyle ZUKOWSKI, Leonardo Kiyosi Bogaz MITSUYUKI, Didier MARGAIRAZ