Patents by Inventor Leonardo Napolitano

Leonardo Napolitano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FLEXIBLE INTERFACE
    Publication number: 20210374023
    Abstract: A system and method are provided on one or more companion chips having a plurality of cores. Each core has core circuitry and a test interface for carrying out tests in relation to the core circuitry. The test interface has an address register to hold an address of the core and address determination circuitry. The address determination circuitry is configured to compare an address received on an address line to the address held in the address register to determine whether a core is being addressed. The address determination circuitry is also configured to direct the test interface to carry out a testing operation in response to the determination.
    Type: Application
    Filed: July 6, 2021
    Publication date: December 2, 2021
    Applicant: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
    Inventors: Leonardo NAPOLITANO, Stephen FIRTH
  • FLEXIBLE INTERFACE
    Publication number: 20160216327
    Abstract: A system and method are provided on one or more companion chips having a plurality of cores. Each core has core circuitry and a test interface for carrying out tests in relation to the core circuitry. The test interface has an address register to hold an address of the core and address determination circuitry. The address determination circuitry is configured to compare an address received on an address line to the address held in the address register to determine whether a core is being addressed. The address determination circuitry is also configured to direct the test interface to carry out a testing operation in response to the determination.
    Type: Application
    Filed: October 3, 2014
    Publication date: July 28, 2016
    Inventors: Leonardo NAPOLITANO, Stephen FIRTH
  • Built-in self-test circuit for phase locked loops, test method and computer program product therefor
    Patent number: 7284173
    Abstract: A built-in self-test circuit for phase locked loops includes a measurement circuit for measuring outputs of the phase locked loops, and receiving as inputs a plurality of external test signals. At least one module includes a scan chain for storing the test signals for programming the phase locked loops and the measurement circuit.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: October 16, 2007
    Assignee: STMicroelectronics S.r.l.
    Inventor: Leonardo Napolitano
  • Built-in self-test circuit for phase locked loops, test method and computer program product therefor
    Publication number: 20050005215
    Abstract: A built-in self-test circuit for phase locked loops includes a measurement circuit for measuring outputs of the phase locked loops, and receiving as inputs a plurality of external test signals. At least one module includes a scan chain for storing the test signals for programming the phase locked loops and the measurement circuit.
    Type: Application
    Filed: May 7, 2004
    Publication date: January 6, 2005
    Applicant: STMicroelectronics S.r.I.
    Inventor: Leonardo Napolitano