Abstract: A memory circuit is provided that includes at least one chain of at least three stages each having a data input, a data output, and a control signal input. Each of the stages between the first stage and the last stage includes a first NMOS transistor having a gate connected to the control signal input of the stage, and a second NMOS transistor having a gate connected to the data input of the stage. The first and second NMOS transistors are serially connected between a first potential and a second potential, with the common electrode of the transistors being connected to the data output of the stage. The data input of the stage is connected to the data output of a preceding one of the stages, and the data output of the stage is connected to the data input of a following one of the stages. Also provided are writing and reading processes for such a memory circuit.