Patents by Inventor Leonardo Valencia Rissetto

Leonardo Valencia Rissetto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11960718
    Abstract: In response to a request to store new data at a memory location of a bitwise programmable non-volatile memory, data stored at the memory location of the bitwise programmable memory is sensed. The bits of the sensed data are compared with bits of the new data. An indication of a cost difference is determined between a first burst of bitwise programming operations associated with programming bits of the new data which are different from bits of the sensed data, and a second burst of bitwise programming operations associated with programming bits of a complementary inversion of the new data which are different from bits of the sensed data. One of the first burst of bitwise programming operations or the second burst of bitwise programming operations is executed based on the generated indication of the cost difference.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: April 16, 2024
    Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS S.r.l.
    Inventors: Leonardo Valencia Rissetto, Francesco Tomaiuolo, Diego De Costantini
  • Publication number: 20220334720
    Abstract: In response to a request to store new data at a memory location of a bitwise programmable non-volatile memory, data stored at the memory location of the bitwise programmable memory is sensed. The bits of the sensed data are compared with bits of the new data. An indication of a cost difference is determined between a first burst of bitwise programming operations associated with programming bits of the new data which are different from bits of the sensed data, and a second burst of bitwise programming operations associated with programming bits of a complementary inversion of the new data which are different from bits of the sensed data. One of the first burst of bitwise programming operations or the second burst of bitwise programming operations is executed based on the generated indication of the cost difference.
    Type: Application
    Filed: April 15, 2022
    Publication date: October 20, 2022
    Applicants: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS S.r.l.
    Inventors: Leonardo VALENCIA RISSETTO, Francesco TOMAIUOLO, Diego DE COSTANTINI
  • Patent number: 10832780
    Abstract: A method can be used for programming a group of memory cells of a non-volatile memory device in a programming window that has a duration longer than a programming duration of a memory cell. The programming window is subdivided into a number of time intervals. A programming profile that was determined by simulation while taking into account a reference criterion is retrieved. The programming profile includes, for each time interval, a maximum number of memory cells that can be triggered for programming within each time interval. The memory device is programmed in the programming window, interval-wise, using the programming profile.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: November 10, 2020
    Assignees: STMICROELECTRONICS (ALPS) SAS, STMICROELECTRONICS (GRENOBLE2) SAS
    Inventors: Leonardo Valencia Rissetto, Elise Le Roux, Christophe Forel
  • Publication number: 20200005872
    Abstract: A method can be used for programming a group of memory cells of a non-volatile memory device in a programming window that has a duration longer than a programming duration of a memory cell. The programming window is subdivided into a number of time intervals. A programming profile that was determined by simulation while taking into account a reference criterion is retrieved. The programming profile includes, for each time interval, a maximum number of memory cells that can be triggered for programming within each time interval. The memory device is programmed in the programming window, interval-wise, using the programming profile.
    Type: Application
    Filed: June 5, 2019
    Publication date: January 2, 2020
    Inventors: Leonardo Valencia Rissetto, Elise Le Roux, Christophe Forel
  • Patent number: 7428178
    Abstract: A memory circuit is provided that includes at least one chain of at least three stages each having a data input, a data output, and a control signal input. Each of the stages between the first stage and the last stage includes a first NMOS transistor having a gate connected to the control signal input of the stage, and a second NMOS transistor having a gate connected to the data input of the stage. The first and second NMOS transistors are serially connected between a first potential and a second potential, with the common electrode of the transistors being connected to the data output of the stage. The data input of the stage is connected to the data output of a preceding one of the stages, and the data output of the stage is connected to the data input of a following one of the stages. Also provided are writing and reading processes for such a memory circuit.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: September 23, 2008
    Assignee: STMicroelectronics SA
    Inventor: Leonardo Valencia Rissetto