Abstract: A circuit which responds to the application of a pulse to its input (6) by generating a pulse at its output (3), the output pulse having a minimum duration T and being extended by the remaining length of the input pulse should the input pulse be still present at the end of the time T, comprises a pair of semiconductor switches (1,2) connecting the output (3) to points (5,4) carrying respective logic levels. The input pulse closes the first switch (1) and also inhibits a gate circuit (9). The resulting logic level on the output (3) closes the second switch (2) after delay by T in a delay circuit (13) and transmission through the gate circuit (9), thereby restoring the original logic level. The instant when this occurs coincides with the presence of the delayed output pulse at the output (14) of the delay circuit and the absence of the pulse at the arrangement input (6). A hold circuit circuit (15) may be provided for holding the logic level currently present at the output (3).

Abstract: An integrated circuit has an internal supply voltage with a positive temperature coefficient, as a result of which the switching rate and the degree of "hot carrier stress" are less sensitive to temperature. By using a reference voltage source having positive temperature coefficient, the normal effects of increasing temperature on switching rate and "hot carrier stress" are compensated for, thus stabilizing circuit operation as a function of temperature. The reference voltage source is incorporated within a voltage converter which is already present in the circuit, to achieve a compact and efficient configuration.

Abstract: An addressable memory unit has address input buffer circuits which output a pair of output connections on which, in read or write mode, two signals which are complementary to one another are present but which may also adopt equal values in such a manner as to cause a predecoder and line selector to select all or none of the selection lines controlling the cells of the memory accessed.

Abstract: When using a laser programmable fuse, a circuit should be 100% stable both before and after the fuse is blown. So far no CMOS circuit can be 100% stable without drawing a constant current. With the "Master fuse Enable" scheme one fuse circuit (master fuse) draws current while disabling all other fuse circuits on-chip. Thus giving 100% stability and reducing power consumption on a chip where no fusing has been done. If, however, one wished to use the rest of the fuses, then the master fuse is blown and all fuse circuits now become active and draw current.

Abstract: An integrated circuit having logic circuits and a logic output buffer, which circuit includes the following sub-circuits: a memory circuit and a logic output circuit, in which no tri-state occurs at the output during a sequence of data signals at the input, wherein the drive of the circuit by means of control signals is not critical over time because the first data signal from the sequence switches off the tri-state mode, the tri-state mode again being introduced if a control signal is furnished, and in the absence of this control signal, the last data signal is retained.

Abstract: A static RAM memory is optimized for speed. The memory is divided into major memory matrices and each major memory matrix is divided into memory blocks. The memory blocks are divided in groups that per group have address bits in common, which however are per group coupled to separate pads or sets of pads. These pads are interconnected on the package to common package pins.

Abstract: An integrated circuit has an on-chip supply voltage reducer, and includes a voltage converter for periodically charging the integrated circuit capacitance. The voltage converter may include a power switching transistor which is connected between an external supply terminal and an internal supply terminal and which is controled by a detector amplifier which senses the voltage across the integrated circuit capacitance connected to the internal supply terminal and which turns the switching transistor on and off depending on the value sensed, with a given hysteresis.

Abstract: Random access memory unit having a plurality of test modes, which is constructed as an integrated circuit and which does not include specific input/output pins to define and to command the passage to test mode. This unit is equipped with means (1) for detecting whether a predefined sequence of logic signals, which is not contained, within a set of sequences which are normally used, but the voltages of which are nevertheless included within the range of voltages which are specified for such signals, is supplied to certain inputs (CE, WE, AO), and for placing the unit in-test mode when such a sequence has been detected. In order to define the nature of the test to be performed, address input terminals, (A1-A8) of the unit are connected to a test mode decoding circuit (2), in which the data applied to the said input terminals are used as data defining the nature of the test to be performed.

Abstract: Data are frequently transmitted via a dual bus line by means of differential signals which are evaluated by a differential amplifier, particularly for reasons of protection against interference. However, such a differential amplifier only has a limited input voltage range, or a dead voltage range of the input signals within which it is not capable of operating. To prevent the voltages on both bus lines from getting into this dead voltage range, either due to a common-mode interference signal on the bus lines or due to a voltage dip in the feed voltage of the differential amplifier, the two bus lines are connected in accordance with the invention to an adjusting circuit which changes the voltages of both bus lines by the same amount in the direction out of the dead voltage range. This prevents unspecified conditions of the differential amplifier without significantly influencing the differential signal on the two bus lines. The application for an integrated memory is described.

Abstract: A push-pull output circuit which is powered by a 5-V supply voltage and in which the "push" part comprises a PMOS transistor and the "pull" comprises a PMOS transistor and an NMOS transistor. The NMOS transistor is driven via a detection circuit so that no hot carrier stress occurs in the NMOS transistor.

Abstract: In relatively large systems of (integrated) circuits, data signals can experience a delay which is in the order of magnitude of a clock-pulse period. The receiving circuit (i.e. receiving the data signal) then receives the data signal too late (the clock pulse has ceased) and can at that moment no longer take over the data signal for further processing or transport. In the system according to the invention the clock pulses are led via a delaying element (for example, the inverting circuits in series) to the receiving circuit (slave of the master/slave flip-flop). The data output of the receiving circuit is connected to a data input of another circuit (master of another master/slave flip-flop), which receives the undelayed clock pulses, the data delay between the receiving circuit and the other circuit being negligible. The data delay is thus distributed over two clock pulses.

Abstract: In a one-electrode/bit SPS CCD memory, a capacity reduction can be obtained by phase shift of one or more clock voltages. For an n-phase system with N groups of n electrodes, the storage capacity can thus be reduced stepwise from at most N(n-1) bits to N(n-2) bits, etc. The stay time of the bits stored is reduced by a corresponding factor, as a result of which the clock frequency in the series registers need not be changed. By this reduction, the memory is more particularly suitable for storing television pictures both in the 625 lines system and in the 525 lines system.

Abstract: Memory cells in an integrated memory circuit are arranged in blocks and selected by block selection gates. This method of activation offers the advantage that the memory cells are accessed faster and that the power consumption is lower than in a memory which is not subdivided into blocks, because only a small group of memory cells is activated per selection operation. A block selection circuit is provided in which selection gates of two neighboring rows of memory cells have one common transistor. As a result of the multiple use of contact areas and the use of a mirror-symmetrical architecture, the lay-out can make optimum use of the available substrate surface area.

Abstract: In a memory cell which is connected between two bit lines, information is stored after selection by causing a first bit line to convey a signal which is complementary to that on a second bit line. It is known, starting from a single data supply line which may convey either a high or a low signal, to provide a memory circuit per column with inverting means so as to be able to charge both bit lines complementarily. Here, this complementary charging is done by connecting, upon selection, the first bit line to the data supply line and connecting a transistor with its main electrodes between ground and the second bit line, which transistor receives the data at its control electrode. This transistor then constitutes, with the bit line load, an inverter. Lay-out aspects relate to the common use of substrate area of two adjacent columns and the common use of a contact in the shown circuit arrangement.

Abstract: In integrated circuits the delay of the signal transitions has to lie within specified limits. This delay is partly determined by variations in the manufacturing process (process scatter). To compensate for the effect of this scatter a load capacitance is connected via a switching element to a node which is to be influenced in the integrated circuit. The switching element receives a reference voltage which is dependent on the manufacturing process and is generated by reference source, so that the node capacitance 26 is connected to the node for a longer or shorter time, depending on the process scatter.

Abstract: The invention relates to a CCD input and reference charge generator, in which the occurrence of electron injection into the substrate (due to cross-talk to the substrate) and hence undesired signal distortions is prevented. For this purpose, the generator is provided with a voltage divider (26) which is constituted at least for a part (28) by a resistance element arranged outside the substrate, for example, by a polycrystalline silicon resistor. Thus, it is achieved that input diode zones (11) are no longer connected to the substrate voltage.

Abstract: Charge-coupled devices are very sensitive to clock cross-talk due to the overlap between successive electrodes. The influence of this cross-talk is reduced when the clock lines are periodically connected to ground by a low-ohmic impedance. For this purpose, each clock line is controlled from a buffer, whose output is connected to a clock line. A clamping transistor is connected between the output and ground. When this clamping transistor is controlled by means of the output signal and at the same time by the input signal of the buffer, the output is clamped to ground at the instant at which the cross-talk is expected by means of only a single clamping transistor.

Abstract: An integrated logic circuit includes a push-pull amplifier stage, in which by means of a bootstrap circuit the potential at the gate of the "push" transistor is brought above the supply voltage so that the output voltage of the amplifier lies above the supply voltage minus the threshold voltage of the push transistor. In order to prevent the charge from leaking away after the bootstrap capacitance has been charged via an enhancement transistor, the enhancement transistor is cut off by means of the "low" input signal. A second bootstrap circuit (between the input and the gate of the enhancement transistor) ensures that the first bootstrap capacitance is charged up to the full supply voltage because the latter gate electrode is lifted above the supply voltage by the second bootstrap.

Abstract: Digital integrated C-MOS circuit in which two cross-coupled P-MOS transistors are connected by two separation transistors (N-MOS) to two complementary switching N-MOS transistor logic networks. The gate electrodes of the separation transistor are connected to a reference voltage source. The switching speed of the C-MOS circuit is increased in that (a) the voltage sweep across the logic networks is reduced; (b) each P-MOS transistor, which is connected by a separation transistor to a junction of the logic network to be charged, is slightly conducting and so is "ready" to charge such junction, and (c) the separation transistor between the fully conducting P-MOS transistor and the junction to be discharged in the second logic network constitutes a high impedance which prevents the conducting P-MOS transistor from charging that junction.

Abstract: A device is described for electronically executing a mathematical operation, being Z=KA+(1-K)B. It is also described how this device or how several of such devices can be used for the design of a number of realizations, such as a recursive filter, a digital mixer etc. The basic idea is the electronic implementation of a mathematical function for binary variables.