Abstract: Various exemplary embodiments relate to improved fabrication of CMOS transistor arrays for integrated circuits. Increased regularity in standard-cells using gate-isolation architecture may permit further reduction in feature size. MOSFETs may be spaced at roughly equal pitch and have increased channel lengths for leakage current reduction. Logic gates may be designed to have nominal channel lengths for speed and increased channel lengths for leakage current reduction. Further leakage current reduction may involve specialized channel lengths for isolation MOSFETs. Thus, the combination of the gate-isolation technique with MOSFETs having lengthened channels that are evenly spaced at substantially the same pitch may produce a flexible library architecture for improved standard-cell designs in advanced CMOS technology nodes.

Abstract: Various exemplary embodiments relate to improved fabrication of CMOS transistor arrays for integrated circuits. Increased regularity in standard-cells using gate-isolation architecture may permit further reduction in feature size. MOSFETs may be spaced at roughly equal pitch and have increased channel lengths for leakage current reduction. Logic gates may be designed to have nominal channel lengths for speed and increased channel lengths for leakage current reduction. Further leakage current reduction may involve specialized channel lengths for isolation MOSFETs. Thus, the combination of the gate-isolation technique with MOSFETs having lengthened channels that are evenly spaced at substantially the same pitch may produce a flexible library architecture for improved standard-cell designs in advanced CMOS technology nodes.

Abstract: The invention relates to a device for parallel data processing, a DSP. The device according to the invention comprises a processor matrix (100) in which processors (103) are arranged in rows (101) and columns (102). Furthermore, the device (100) comprises first and second external data ports (107, 108). The rows (101) arranged in a stepwise manner and the columns are arranged in a stepwise manner. The processors (103) have a first processor data port (104), which is connected with one of the first external data ports (107) by means of first essentially straight connection. The processors (103) further comprise a second processor data port (105), which is connected with one of the second external data ports (108) by means of an essentially straight second connection (110). The first connection (107) and the second connection (108) are oriented substantially orthogonal to each other.

Abstract: The invention relates to a device for parallel processing data and to a camera system comprising such a device. The camera system (1) comprises a sensor matrix (2), a data converter (3), a DSP (4), a central controller (5), a data buffer (7) and a processor matrix (11) consisting of processors (12). The sensor matrix (2) converts incident electromagnetic radiation into pixel signals. The data converter (3) converts the pixel signals into data. The arrows (6) and (8) diagrammatically indicate the transport of pixel signals and data. The data buffer (7) is physically divided into a part (7A) and a part (7B) and functionally divided into an I/O register (9) and a memory bank (10). The central controller (5) co-ordinates the different tasks. The processors (12) and the data buffer (7) have data ports (13) and further data ports (14) with inputs and outputs which are mutually connected in an electrically conducting manner using the connections (15).

Abstract: The invention relates to a device for parallel processing data and to a camera system comprising such a device. The camera system (1) comprises a sensor matrix (2), a data converter (3), a DSP (4), a central controller (5), a data buffer (7) and a processor matrix (11) consisting of processors (12). The sensor matrix (2) converts incident electromagnetic radiation into pixel signals. The data converter (3) converts the pixel signals into data. The arrows (6) and (8) diagrammatically indicate the transport of pixel signals and data. The data buffer (7) is physically divided into a part (7A) and a part (7B) and functionally divided into an I/O register (9) and a memory bank (10). The central controller (5) co-ordinates the different tasks. The processors (12) and the data buffer (7) have data ports (13) and further data ports (14) with inputs and outputs which are mutually connected in an electrically conducting manner by means of the connections (15).

Abstract: The invention relates to a display system comprising a display device capable of displaying information in multiple windows of the display device, enabling the user to select a window for controlling a parameter of said window in response to subsequent user supplied parameter control commands. The display system according to the invention comprises two or more remote controls, and association means for associating a respective remote control with a respective window. Upon reception of a control command from a remote control, the window associated with the remote control is selected, and the control command is applied to the selected window. In this way, multiple users are enabled to independently control a window displayed on the display device.