Patents by Inventor Leonardus Petrus Kouwenhoven

Leonardus Petrus Kouwenhoven has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240107897
    Abstract: A fabrication method comprising: forming a mask of an amorphous material over a crystalline surface of a substrate, the mask having a pattern of openings defining areas of an active region in which one or more components of one or more active devices are to be formed, the mask further defining a non-active region in which no active devices are to be formed; and forming a deposition material through the mask by an epitaxial growth process. The deposition material thus forms in the openings of the active region. The pattern of openings through the mask further comprises one or more reservoirs formed in the non-active region, each of the reservoirs being connected by the pattern of openings in the mask to at least one of the areas in the active region, and the deposition material forming in the reservoirs as part of the epitaxial growth.
    Type: Application
    Filed: September 10, 2019
    Publication date: March 28, 2024
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Pavel ASEEV, Philippe CAROFF-GAONAC'H, Leonardus Petrus KOUWENHOVEN
  • Patent number: 11737377
    Abstract: A method of fabricating a device, comprising forming portions of electronic circuitry and a shadow wall structure over a substrate, and subsequently depositing a conducting layer over the substrate by angled deposition of a conducting material in at least a first deposition direction at an acute angle relative to the plane of the substrate. The shadow wall structure is arranged to cast a shadow in the deposition, leaving areas where the conducting material is not deposited. The shadow wall structure comprises one or more gaps each shorter than a shadow length of a respective part of the shadow wall structure casting the shadow into the gap, to prevent the conducting material forming in the gaps and to thereby create regions of said upper conducting layer that are electrically isolated from one another. These are arranged to form conducting elements for applying signals to, and/or receiving signals from, the electronic circuitry.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: August 22, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sebastian Heedt, Marina Quintero-Pérez, Francesco Borsoi, Kevin Alexander Van Hoogdalen, Leonardus Petrus Kouwenhoven
  • Publication number: 20220149261
    Abstract: A method of fabricating a device, comprising forming portions of electronic circuitry and a shadow wall structure over a substrate, and subsequently depositing a conducting layer over the substrate by angled deposition of a conducting material in at least a first deposition direction at an acute angle relative to the plane of the substrate. The shadow wall structure is arranged to cast a shadow in the deposition, leaving areas where the conducting material is not deposited. The shadow wall structure comprises one or more gaps each shorter than a shadow length of a respective part of the shadow wall structure casting the shadow into the gap, to prevent the conducting material forming in the gaps and to thereby create regions of said upper conducting layer that are electrically isolated from one another. These are arranged to form conducting elements for applying signals to, and/or receiving signals from, the electronic circuitry.
    Type: Application
    Filed: February 15, 2019
    Publication date: May 12, 2022
    Applicants: Microsoft Technology Licensing, LLC, Delft University of Technology
    Inventors: Sebastian HEEDT, Marina QUINTERO-PÉREZ, Francesco BORSOI, Kevin Alexander VAN HOOGDALEN, Leonardus Petrus KOUWENHOVEN
  • Publication number: 20210126180
    Abstract: A semiconductor-superconductor hybrid device comprises a semiconductor layer and a superconductor layer. The superconductor layer is arranged over an edge of the semiconductor layer so as to enable energy level hybridisation between the semiconductor layer and the superconductor layer. The semiconductor layer is arranged in a sandwich structure between first and second insulating layers, each insulating layer being in contact with a respective opposed face of the semiconductor layer. This configuration may allow for good control over the geometry of the semiconductor layer and may improve tolerance to manufacturing variations. The device may be useful in a quantum computer. Also provided is a method of manufacturing the device, and a method of inducing topological behaviour in the device.
    Type: Application
    Filed: October 24, 2019
    Publication date: April 29, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Georg Wolfgang Winkler, Roman Mykolayovych Lutchyn, Leonardus Petrus Kouwenhoven, Farhad Karimi