Abstract: The invention relates to a device for parallel data processing, a DSP. The device according to the invention comprises a processor matrix (100) in which processors (103) are arranged in rows (101) and columns (102). Furthermore, the device (100) comprises first and second external data ports (107, 108). The rows (101) arranged in a stepwise manner and the columns are arranged in a stepwise manner. The processors (103) have a first processor data port (104), which is connected with one of the first external data ports (107) by means of first essentially straight connection. The processors (103) further comprise a second processor data port (105), which is connected with one of the second external data ports (108) by means of an essentially straight second connection (110). The first connection (107) and the second connection (108) are oriented substantially orthogonal to each other.

Abstract: A data processing device contains a time division multiplexed multiport memory. The timing of memory access is defined in time-slots for access to the memory from respective ports. Timing is generated asynchronously with a handshake in response to a ready signal indicating completion of access during a previous time-slot.